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794 lines
12 KiB
794 lines
12 KiB
/* |
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* Copyright (c) 2021 Intel Corporation. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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|
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#include <zephyr/kernel.h> |
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#include <xtensa_asm2_context.h> |
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#include <zephyr/debug/gdbstub.h> |
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#include <zephyr/offsets.h> |
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|
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/* |
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* Address Mappings From ESP32 Technical Reference Manual Version 4.5 |
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* https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf |
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*/ |
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const struct gdb_mem_region gdb_mem_region_array[] = { |
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{ |
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/* External Memory (Data Bus) */ |
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.start = 0x3F400000, |
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.end = 0x3FBFFFFF, |
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.attributes = GDB_MEM_REGION_RW, |
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.alignment = 4, |
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}, |
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{ |
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/* Peripheral (Data Bus) */ |
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.start = 0x3FF00000, |
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.end = 0x3FF7FFFF, |
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.attributes = GDB_MEM_REGION_RW, |
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.alignment = 4, |
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}, |
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{ |
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/* RTC FAST Memory (Data Bus) */ |
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.start = 0x3FF80000, |
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.end = 0x3FF81FFF, |
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.attributes = GDB_MEM_REGION_RW, |
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.alignment = 4, |
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}, |
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{ |
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/* Internal ROM 1 (Data Bus) */ |
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.start = 0x3FF90000, |
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.end = 0x3FF9FFFF, |
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.attributes = GDB_MEM_REGION_RO, |
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.alignment = 4, |
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}, |
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{ |
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/* Internal SRAM 1 and 2 (Data Bus) */ |
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.start = 0x3FFAE000, |
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.end = 0x3FFFFFFF, |
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.attributes = GDB_MEM_REGION_RW, |
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.alignment = 4, |
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}, |
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{ |
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/* Internal ROM 0 (Instruction Bus) */ |
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.start = 0x40000000, |
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.end = 0x4005FFFF, |
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.attributes = GDB_MEM_REGION_RO, |
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.alignment = 4, |
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}, |
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{ |
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/* Internal SRAM 0 and 1 (Instruction Bus) */ |
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.start = 0x40070000, |
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.end = 0x400BFFFF, |
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.attributes = GDB_MEM_REGION_RW, |
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.alignment = 4, |
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}, |
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{ |
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/* RTC FAST Memory (Instruction Bus) */ |
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.start = 0x400C0000, |
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.end = 0x400C1FFF, |
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.attributes = GDB_MEM_REGION_RW, |
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.alignment = 4, |
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}, |
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{ |
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/* External Memory (Instruction Bus) */ |
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.start = 0x400C2000, |
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.end = 0x400CFFFF, |
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.attributes = GDB_MEM_REGION_RW, |
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.alignment = 4, |
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}, |
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{ |
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/* |
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* Flash memory obtained via GDB memory map |
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* with ESP32's OpenOCD |
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*/ |
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.start = 0x400D0000, |
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.end = 0x400D5FFF, |
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.attributes = GDB_MEM_REGION_RO, |
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.alignment = 4, |
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}, |
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{ |
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/* External Memory (Instruction Bus) */ |
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.start = 0x400D6000, |
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.end = 0x40BFFFFF, |
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.attributes = GDB_MEM_REGION_RW, |
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.alignment = 4, |
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}, |
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{ |
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/* RTC SLOW Memory (Data/Instruction Bus) */ |
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.start = 0x50000000, |
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.end = 0x50001FFF, |
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.attributes = GDB_MEM_REGION_RW, |
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.alignment = 4, |
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}, |
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}; |
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const size_t gdb_mem_num_regions = ARRAY_SIZE(gdb_mem_region_array); |
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static struct xtensa_register gdb_reg_list[] = { |
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{ |
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/* PC */ |
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.idx = 0, |
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.regno = 0x0020, |
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.byte_size = 4, |
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.gpkt_offset = 0, |
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.stack_offset = ___xtensa_irq_bsa_t_pc_OFFSET, |
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}, |
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{ |
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/* AR0 */ |
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.idx = 1, |
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.regno = 0x100, |
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.byte_size = 4, |
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.gpkt_offset = 4, |
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}, |
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{ |
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/* AR1 */ |
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.idx = 2, |
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.regno = 0x101, |
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.byte_size = 4, |
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.gpkt_offset = 8, |
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}, |
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{ |
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/* AR2 */ |
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.idx = 3, |
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.regno = 0x102, |
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.byte_size = 4, |
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.gpkt_offset = 12, |
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}, |
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{ |
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/* AR3 */ |
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.idx = 4, |
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.regno = 0x103, |
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.byte_size = 4, |
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.gpkt_offset = 16, |
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}, |
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{ |
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/* AR4 */ |
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.idx = 5, |
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.regno = 0x104, |
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.byte_size = 4, |
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.gpkt_offset = 20, |
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}, |
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{ |
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/* AR5 */ |
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.idx = 6, |
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.regno = 0x105, |
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.byte_size = 4, |
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.gpkt_offset = 24, |
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}, |
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{ |
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/* AR6 */ |
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.idx = 7, |
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.regno = 0x106, |
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.byte_size = 4, |
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.gpkt_offset = 28, |
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}, |
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{ |
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/* AR7 */ |
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.idx = 8, |
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.regno = 0x107, |
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.byte_size = 4, |
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.gpkt_offset = 32, |
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}, |
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{ |
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/* AR8 */ |
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.idx = 9, |
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.regno = 0x108, |
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.byte_size = 4, |
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.gpkt_offset = 36, |
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}, |
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{ |
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/* AR9 */ |
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.idx = 10, |
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.regno = 0x109, |
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.byte_size = 4, |
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.gpkt_offset = 40, |
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}, |
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{ |
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/* AR10 */ |
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.idx = 11, |
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.regno = 0x10a, |
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.byte_size = 4, |
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.gpkt_offset = 44, |
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}, |
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{ |
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/* AR11 */ |
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.idx = 12, |
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.regno = 0x10b, |
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.byte_size = 4, |
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.gpkt_offset = 48, |
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}, |
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{ |
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/* AR12 */ |
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.idx = 13, |
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.regno = 0x10c, |
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.byte_size = 4, |
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.gpkt_offset = 52, |
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}, |
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{ |
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/* AR13 */ |
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.idx = 14, |
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.regno = 0x10d, |
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.byte_size = 4, |
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.gpkt_offset = 56, |
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}, |
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{ |
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/* AR14 */ |
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.idx = 15, |
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.regno = 0x10e, |
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.byte_size = 4, |
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.gpkt_offset = 60, |
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}, |
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{ |
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/* AR15 */ |
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.idx = 16, |
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.regno = 0x10f, |
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.byte_size = 4, |
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.gpkt_offset = 64, |
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}, |
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{ |
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/* AR16 */ |
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.idx = 17, |
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.regno = 0x110, |
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.byte_size = 4, |
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.gpkt_offset = 68, |
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}, |
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{ |
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/* AR17 */ |
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.idx = 18, |
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.regno = 0x111, |
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.byte_size = 4, |
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.gpkt_offset = 72, |
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}, |
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{ |
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/* AR18 */ |
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.idx = 19, |
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.regno = 0x112, |
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.byte_size = 4, |
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.gpkt_offset = 76, |
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}, |
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{ |
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/* AR19 */ |
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.idx = 20, |
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.regno = 0x113, |
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.byte_size = 4, |
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.gpkt_offset = 80, |
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}, |
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{ |
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/* AR20 */ |
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.idx = 21, |
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.regno = 0x114, |
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.byte_size = 4, |
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.gpkt_offset = 84, |
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}, |
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{ |
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/* AR21 */ |
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.idx = 22, |
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.regno = 0x115, |
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.byte_size = 4, |
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.gpkt_offset = 88, |
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}, |
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{ |
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/* AR22 */ |
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.idx = 23, |
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.regno = 0x116, |
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.byte_size = 4, |
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.gpkt_offset = 92, |
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}, |
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{ |
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/* AR23 */ |
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.idx = 24, |
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.regno = 0x117, |
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.byte_size = 4, |
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.gpkt_offset = 96, |
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}, |
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{ |
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/* AR24 */ |
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.idx = 25, |
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.regno = 0x118, |
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.byte_size = 4, |
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.gpkt_offset = 100, |
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}, |
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{ |
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/* AR25 */ |
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.idx = 26, |
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.regno = 0x119, |
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.byte_size = 4, |
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.gpkt_offset = 104, |
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}, |
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{ |
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/* AR26 */ |
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.idx = 27, |
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.regno = 0x11a, |
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.byte_size = 4, |
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.gpkt_offset = 108, |
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}, |
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{ |
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/* AR27 */ |
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.idx = 28, |
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.regno = 0x11b, |
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.byte_size = 4, |
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.gpkt_offset = 112, |
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}, |
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{ |
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/* AR28 */ |
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.idx = 29, |
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.regno = 0x11c, |
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.byte_size = 4, |
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.gpkt_offset = 116, |
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}, |
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{ |
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/* AR29 */ |
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.idx = 30, |
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.regno = 0x11d, |
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.byte_size = 4, |
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.gpkt_offset = 120, |
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}, |
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{ |
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/* AR30 */ |
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.idx = 31, |
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.regno = 0x11e, |
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.byte_size = 4, |
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.gpkt_offset = 124, |
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}, |
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{ |
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/* AR31 */ |
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.idx = 32, |
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.regno = 0x11f, |
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.byte_size = 4, |
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.gpkt_offset = 128, |
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}, |
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{ |
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/* AR32 */ |
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.idx = 33, |
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.regno = 0x120, |
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.byte_size = 4, |
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.gpkt_offset = 132, |
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}, |
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{ |
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/* AR33 */ |
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.idx = 34, |
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.regno = 0x121, |
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.byte_size = 4, |
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.gpkt_offset = 136, |
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}, |
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{ |
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/* AR34 */ |
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.idx = 35, |
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.regno = 0x122, |
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.byte_size = 4, |
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.gpkt_offset = 140, |
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}, |
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{ |
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/* AR35 */ |
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.idx = 36, |
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.regno = 0x123, |
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.byte_size = 4, |
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.gpkt_offset = 144, |
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}, |
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{ |
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/* AR36 */ |
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.idx = 37, |
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.regno = 0x124, |
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.byte_size = 4, |
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.gpkt_offset = 148, |
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}, |
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{ |
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/* AR37 */ |
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.idx = 38, |
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.regno = 0x125, |
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.byte_size = 4, |
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.gpkt_offset = 152, |
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}, |
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{ |
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/* AR38 */ |
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.idx = 39, |
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.regno = 0x126, |
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.byte_size = 4, |
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.gpkt_offset = 156, |
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}, |
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{ |
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/* AR39 */ |
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.idx = 40, |
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.regno = 0x127, |
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.byte_size = 4, |
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.gpkt_offset = 160, |
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}, |
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{ |
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/* AR40 */ |
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.idx = 41, |
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.regno = 0x128, |
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.byte_size = 4, |
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.gpkt_offset = 164, |
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}, |
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{ |
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/* AR41 */ |
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.idx = 42, |
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.regno = 0x129, |
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.byte_size = 4, |
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.gpkt_offset = 168, |
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}, |
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{ |
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/* AR42 */ |
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.idx = 43, |
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.regno = 0x12a, |
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.byte_size = 4, |
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.gpkt_offset = 172, |
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}, |
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{ |
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/* AR43 */ |
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.idx = 44, |
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.regno = 0x12b, |
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.byte_size = 4, |
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.gpkt_offset = 176, |
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}, |
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{ |
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/* AR44 */ |
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.idx = 45, |
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.regno = 0x12c, |
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.byte_size = 4, |
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.gpkt_offset = 180, |
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}, |
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{ |
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/* AR45 */ |
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.idx = 46, |
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.regno = 0x12d, |
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.byte_size = 4, |
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.gpkt_offset = 184, |
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}, |
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{ |
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/* AR46 */ |
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.idx = 47, |
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.regno = 0x12e, |
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.byte_size = 4, |
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.gpkt_offset = 188, |
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}, |
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{ |
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/* AR47 */ |
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.idx = 48, |
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.regno = 0x12f, |
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.byte_size = 4, |
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.gpkt_offset = 192, |
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}, |
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{ |
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/* AR48 */ |
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.idx = 49, |
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.regno = 0x130, |
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.byte_size = 4, |
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.gpkt_offset = 196, |
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}, |
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{ |
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/* AR49 */ |
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.idx = 50, |
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.regno = 0x131, |
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.byte_size = 4, |
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.gpkt_offset = 200, |
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}, |
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{ |
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/* AR50 */ |
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.idx = 51, |
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.regno = 0x132, |
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.byte_size = 4, |
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.gpkt_offset = 204, |
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}, |
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{ |
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/* AR51 */ |
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.idx = 52, |
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.regno = 0x133, |
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.byte_size = 4, |
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.gpkt_offset = 208, |
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}, |
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{ |
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/* AR52 */ |
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.idx = 53, |
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.regno = 0x134, |
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.byte_size = 4, |
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.gpkt_offset = 212, |
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}, |
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{ |
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/* AR53 */ |
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.idx = 54, |
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.regno = 0x135, |
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.byte_size = 4, |
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.gpkt_offset = 216, |
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}, |
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{ |
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/* AR54 */ |
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.idx = 55, |
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.regno = 0x136, |
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.byte_size = 4, |
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.gpkt_offset = 220, |
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}, |
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{ |
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/* AR55 */ |
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.idx = 56, |
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.regno = 0x137, |
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.byte_size = 4, |
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.gpkt_offset = 224, |
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}, |
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{ |
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/* AR56 */ |
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.idx = 57, |
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.regno = 0x138, |
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.byte_size = 4, |
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.gpkt_offset = 228, |
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}, |
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{ |
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/* AR57 */ |
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.idx = 58, |
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.regno = 0x139, |
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.byte_size = 4, |
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.gpkt_offset = 232, |
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}, |
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{ |
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/* AR58 */ |
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.idx = 59, |
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.regno = 0x13a, |
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.byte_size = 4, |
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.gpkt_offset = 236, |
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}, |
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{ |
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/* AR59 */ |
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.idx = 60, |
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.regno = 0x13b, |
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.byte_size = 4, |
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.gpkt_offset = 240, |
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}, |
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{ |
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/* AR60 */ |
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.idx = 61, |
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.regno = 0x13c, |
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.byte_size = 4, |
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.gpkt_offset = 244, |
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}, |
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{ |
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/* AR61 */ |
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.idx = 62, |
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.regno = 0x13d, |
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.byte_size = 4, |
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.gpkt_offset = 248, |
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}, |
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{ |
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/* AR62 */ |
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.idx = 63, |
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.regno = 0x13e, |
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.byte_size = 4, |
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.gpkt_offset = 252, |
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}, |
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{ |
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/* AR63 */ |
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.idx = 64, |
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.regno = 0x13f, |
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.byte_size = 4, |
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.gpkt_offset = 256, |
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}, |
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{ |
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/* LBEG */ |
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.idx = 65, |
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.regno = 0x0200, |
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.byte_size = 4, |
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.gpkt_offset = 260, |
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.stack_offset = ___xtensa_irq_bsa_t_lbeg_OFFSET, |
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}, |
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{ |
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/* LEND */ |
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.idx = 66, |
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.regno = 0x0201, |
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.byte_size = 4, |
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.gpkt_offset = 264, |
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.stack_offset = ___xtensa_irq_bsa_t_lend_OFFSET, |
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}, |
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{ |
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/* LCOUNT */ |
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.idx = 67, |
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.regno = 0x0202, |
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.byte_size = 4, |
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.gpkt_offset = 268, |
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.stack_offset = ___xtensa_irq_bsa_t_lcount_OFFSET, |
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}, |
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{ |
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/* SAR */ |
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.idx = 68, |
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.regno = 0x0203, |
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.byte_size = 4, |
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.gpkt_offset = 272, |
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.stack_offset = ___xtensa_irq_bsa_t_sar_OFFSET, |
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}, |
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{ |
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/* WINDOWBASE */ |
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.idx = 69, |
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.regno = 0x0248, |
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.byte_size = 4, |
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.gpkt_offset = 276, |
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.is_read_only = 1, |
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}, |
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{ |
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/* WINDOWSTART */ |
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.idx = 70, |
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.regno = 0x0249, |
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.byte_size = 4, |
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.gpkt_offset = 280, |
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.is_read_only = 1, |
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}, |
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{ |
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/* PS */ |
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.idx = 73, |
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.regno = 0x02E6, |
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.byte_size = 4, |
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.gpkt_offset = 292, |
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.stack_offset = ___xtensa_irq_bsa_t_ps_OFFSET, |
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}, |
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{ |
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/* THREADPTR */ |
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.idx = 74, |
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.regno = 0x02E7, |
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.byte_size = 4, |
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.gpkt_offset = 296, |
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#ifdef CONFIG_THREAD_LOCAL_STORAGE |
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/* Only saved in stack if TLS is enabled */ |
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.stack_offset = ___xtensa_irq_bsa_t_threadptr_OFFSET, |
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#endif |
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}, |
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{ |
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/* SCOMPARE1 */ |
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.idx = 76, |
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.regno = 0x020C, |
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.byte_size = 4, |
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.gpkt_offset = 304, |
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.stack_offset = ___xtensa_irq_bsa_t_scompare1_OFFSET, |
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}, |
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{ |
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/* EXCCAUSE */ |
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.idx = 143, |
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.regno = 0x02E8, |
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.byte_size = 4, |
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.gpkt_offset = 572, |
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.stack_offset = ___xtensa_irq_bsa_t_exccause_OFFSET, |
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}, |
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{ |
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/* DEBUGCAUSE */ |
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.idx = 144, |
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.regno = 0x02E9, |
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.byte_size = 4, |
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.gpkt_offset = 576, |
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}, |
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{ |
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/* EXCVADDR */ |
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.idx = 149, |
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.regno = 0x02EE, |
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.byte_size = 4, |
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.gpkt_offset = 596, |
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}, |
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{ |
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/* A0 */ |
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.idx = 157, |
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.regno = 0x0000, |
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.byte_size = 4, |
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.gpkt_offset = 628, |
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.stack_offset = ___xtensa_irq_bsa_t_a0_OFFSET, |
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}, |
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{ |
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/* A1 */ |
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.idx = 158, |
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.regno = 0x0001, |
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.byte_size = 4, |
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.gpkt_offset = 632, |
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}, |
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{ |
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/* A2 */ |
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.idx = 159, |
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.regno = 0x0002, |
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.byte_size = 4, |
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.gpkt_offset = 636, |
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.stack_offset = ___xtensa_irq_bsa_t_a2_OFFSET, |
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}, |
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{ |
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/* A3 */ |
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.idx = 160, |
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.regno = 0x0003, |
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.byte_size = 4, |
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.gpkt_offset = 640, |
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.stack_offset = ___xtensa_irq_bsa_t_a3_OFFSET, |
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}, |
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{ |
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/* A4 */ |
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.idx = 161, |
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.regno = 0x0004, |
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.byte_size = 4, |
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.gpkt_offset = 644, |
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.stack_offset = -16, |
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}, |
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{ |
|
/* A5 */ |
|
.idx = 162, |
|
.regno = 0x0005, |
|
.byte_size = 4, |
|
.gpkt_offset = 648, |
|
.stack_offset = -12, |
|
}, |
|
{ |
|
/* A6 */ |
|
.idx = 163, |
|
.regno = 0x0006, |
|
.byte_size = 4, |
|
.gpkt_offset = 652, |
|
.stack_offset = -8, |
|
}, |
|
{ |
|
/* A7 */ |
|
.idx = 164, |
|
.regno = 0x0007, |
|
.byte_size = 4, |
|
.gpkt_offset = 656, |
|
.stack_offset = -4, |
|
}, |
|
{ |
|
/* A8 */ |
|
.idx = 165, |
|
.regno = 0x0008, |
|
.byte_size = 4, |
|
.gpkt_offset = 660, |
|
.stack_offset = -32, |
|
}, |
|
{ |
|
/* A9 */ |
|
.idx = 166, |
|
.regno = 0x0009, |
|
.byte_size = 4, |
|
.gpkt_offset = 664, |
|
.stack_offset = -28, |
|
}, |
|
{ |
|
/* A10 */ |
|
.idx = 167, |
|
.regno = 0x000A, |
|
.byte_size = 4, |
|
.gpkt_offset = 668, |
|
.stack_offset = -24, |
|
}, |
|
{ |
|
/* A11 */ |
|
.idx = 168, |
|
.regno = 0x000B, |
|
.byte_size = 4, |
|
.gpkt_offset = 672, |
|
.stack_offset = -20, |
|
}, |
|
{ |
|
/* A12 */ |
|
.idx = 169, |
|
.regno = 0x000C, |
|
.byte_size = 4, |
|
.gpkt_offset = 676, |
|
.stack_offset = -48, |
|
}, |
|
{ |
|
/* A13 */ |
|
.idx = 170, |
|
.regno = 0x000D, |
|
.byte_size = 4, |
|
.gpkt_offset = 680, |
|
.stack_offset = -44, |
|
}, |
|
{ |
|
/* A14 */ |
|
.idx = 171, |
|
.regno = 0x000E, |
|
.byte_size = 4, |
|
.gpkt_offset = 684, |
|
.stack_offset = -40, |
|
}, |
|
{ |
|
/* A15 */ |
|
.idx = 172, |
|
.regno = 0x000F, |
|
.byte_size = 4, |
|
.gpkt_offset = 688, |
|
.stack_offset = -36, |
|
}, |
|
}; |
|
|
|
struct gdb_ctx xtensa_gdb_ctx = { |
|
.regs = gdb_reg_list, |
|
.num_regs = ARRAY_SIZE(gdb_reg_list), |
|
};
|
|
|