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56 lines
1.4 KiB
56 lines
1.4 KiB
/* |
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* Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_DRIVERS_SPI_ESP32_SPIM_H_ |
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#define ZEPHYR_DRIVERS_SPI_ESP32_SPIM_H_ |
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#define SPI_MASTER_FREQ_8M (APB_CLK_FREQ/10) |
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#define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) /* 8.89MHz */ |
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#define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) /* 10MHz */ |
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#define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) /* 11.43MHz */ |
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#define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) /* 13.33MHz */ |
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#define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) /* 16MHz */ |
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#define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) /* 20MHz */ |
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#define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) /* 26.67MHz */ |
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#define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) /* 40MHz */ |
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#define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */ |
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struct spi_esp32_config { |
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spi_dev_t *spi; |
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const struct device *clock_dev; |
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int frequency; |
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int duty_cycle; |
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int input_delay_ns; |
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int irq_source; |
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clock_control_subsys_t clock_subsys; |
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struct { |
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int miso_s; |
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int mosi_s; |
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int sclk_s; |
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int csel_s; |
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} signals; |
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struct { |
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int miso; |
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int mosi; |
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int sclk; |
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int csel; |
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} pins; |
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}; |
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struct spi_esp32_data { |
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struct spi_context ctx; |
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spi_hal_context_t hal; |
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spi_hal_timing_conf_t timing_config; |
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spi_hal_dev_config_t dev_config; |
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spi_hal_trans_config_t trans_config; |
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uint8_t dfs; |
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int irq_line; |
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}; |
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#endif /* ZEPHYR_DRIVERS_SPI_ESP32_SPIM_H_ */
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