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64 lines
1.7 KiB
64 lines
1.7 KiB
# STM32 I2S driver configuration options |
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# Copyright (c) 2018 STMicroelectronics |
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# SPDX-License-Identifier: Apache-2.0 |
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menuconfig I2S_STM32 |
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bool "STM32 MCU I2S controller driver" |
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depends on SOC_SERIES_STM32F4X |
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select DMA |
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help |
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Enable I2S support on the STM32 family of processors. |
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(Tested on the STM32F4 series) |
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if I2S_STM32 |
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config I2S_STM32_RX_BLOCK_COUNT |
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int "RX queue length" |
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default 4 |
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config I2S_STM32_TX_BLOCK_COUNT |
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int "TX queue length" |
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default 4 |
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config I2S_STM32_USE_PLLI2S_ENABLE |
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bool "Enable usage of PLL" |
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help |
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Enable it if I2S clock should be provided by the PLLI2S. |
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If not enabled the clock will be provided by HSI/HSE. |
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config I2S_STM32_PLLI2S_PLLM |
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int "Division factor for PLLI2S VCO input clock" |
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depends on I2S_STM32_USE_PLLI2S_ENABLE |
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default 8 |
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range 2 63 |
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help |
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Division factor for the audio PLL (PLLI2S) VCO input clock. |
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PLLM factor should be selected to ensure that the VCO |
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input frequency ranges from 1 to 2 MHz. It is recommended |
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to select a frequency of 2 MHz to limit PLL jitter. |
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Allowed values: 2-63 |
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config I2S_STM32_PLLI2S_PLLN |
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int "Multiplier factor for PLLI2S VCO output clock" |
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depends on I2S_STM32_USE_PLLI2S_ENABLE |
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default 56 |
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range 50 432 |
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help |
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Multiply factor for the audio PLL (PLLI2S) VCO output clock. |
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PLLN factor should be selected to ensure that the VCO |
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output frequency ranges from 100 to 432 MHz. |
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Allowed values: 50-432 |
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config I2S_STM32_PLLI2S_PLLR |
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int "Division factor for I2S clock" |
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depends on I2S_STM32_USE_PLLI2S_ENABLE |
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default 7 |
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range 2 7 |
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help |
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Division factor for the I2S clock. |
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PLLR factor should be selected to ensure that the I2S clock |
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frequency is less than or equal to 192MHz. |
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Allowed values: 2-7 |
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endif # I2S_STM32
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