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248 lines
6.3 KiB
248 lines
6.3 KiB
/* |
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* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com> |
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* Copyright (c) 2017 Linaro Limited |
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* Copyright (c) 2017 BayLibre, SAS |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define LOG_DOMAIN flash_stm32g0 |
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#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL |
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#include <logging/log.h> |
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LOG_MODULE_REGISTER(LOG_DOMAIN); |
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#include <kernel.h> |
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#include <device.h> |
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#include <string.h> |
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#include <drivers/flash.h> |
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#include <init.h> |
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#include <soc.h> |
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#include "flash_stm32.h" |
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/* FLASH_DBANK_SUPPORT is defined in the HAL for all G0Bx and G0C1 SoCs, |
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* while only those with 256KiB and 512KiB Flash have two banks. |
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*/ |
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#if defined(FLASH_DBANK_SUPPORT) && (CONFIG_FLASH_SIZE > (128)) |
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#define STM32G0_DBANK_SUPPORT |
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#endif |
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#if defined(STM32G0_DBANK_SUPPORT) |
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#define STM32G0_BANK_COUNT 2 |
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#define STM32G0_BANK2_START_PAGE_NR 256 |
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#else |
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#define STM32G0_BANK_COUNT 1 |
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#endif |
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#define STM32G0_FLASH_SIZE (FLASH_SIZE) |
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#define STM32G0_FLASH_PAGE_SIZE (FLASH_PAGE_SIZE) |
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#define STM32G0_PAGES_PER_BANK \ |
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((STM32G0_FLASH_SIZE / STM32G0_FLASH_PAGE_SIZE) / STM32G0_BANK_COUNT) |
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/* |
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* offset and len must be aligned on 8 for write, |
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* positive and not beyond end of flash |
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* On dual-bank SoCs memory accesses starting on the first bank and continuing |
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* beyond the first bank into the second bank are allowed. |
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*/ |
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bool flash_stm32_valid_range(const struct device *dev, off_t offset, |
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uint32_t len, |
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bool write) |
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{ |
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return (!write || (offset % 8 == 0 && len % 8 == 0)) && |
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flash_stm32_range_exists(dev, offset, len); |
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} |
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static inline void flush_cache(FLASH_TypeDef *regs) |
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{ |
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if (regs->ACR & FLASH_ACR_ICEN) { |
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regs->ACR &= ~FLASH_ACR_ICEN; |
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/* Datasheet: ICRST: Instruction cache reset : |
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* This bit can be written only when the instruction cache |
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* is disabled |
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*/ |
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regs->ACR |= FLASH_ACR_ICRST; |
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regs->ACR &= ~FLASH_ACR_ICRST; |
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regs->ACR |= FLASH_ACR_ICEN; |
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} |
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} |
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static int write_dword(const struct device *dev, off_t offset, uint64_t val) |
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{ |
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volatile uint32_t *flash = (uint32_t *)(offset + CONFIG_FLASH_BASE_ADDRESS); |
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); |
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uint32_t tmp; |
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int rc; |
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/* if the control register is locked, do not fail silently */ |
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if (regs->CR & FLASH_CR_LOCK) { |
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return -EIO; |
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} |
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/* Check that no Flash main memory operation is ongoing */ |
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rc = flash_stm32_wait_flash_idle(dev); |
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if (rc < 0) { |
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return rc; |
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} |
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/* Check if this double word is erased */ |
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if (flash[0] != 0xFFFFFFFFUL || |
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flash[1] != 0xFFFFFFFFUL) { |
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return -EIO; |
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} |
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/* Set the PG bit */ |
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regs->CR |= FLASH_CR_PG; |
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/* Flush the register write */ |
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tmp = regs->CR; |
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/* Perform the data write operation at the desired memory address */ |
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flash[0] = (uint32_t)val; |
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flash[1] = (uint32_t)(val >> 32); |
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/* Wait until the BSY bit is cleared */ |
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rc = flash_stm32_wait_flash_idle(dev); |
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/* Clear the PG bit */ |
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regs->CR &= (~FLASH_CR_PG); |
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return rc; |
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} |
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static int erase_page(const struct device *dev, unsigned int offset) |
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{ |
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); |
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uint32_t tmp; |
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int rc; |
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int page; |
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/* if the control register is locked, do not fail silently */ |
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if (regs->CR & FLASH_CR_LOCK) { |
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return -EIO; |
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} |
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/* Check that no Flash memory operation is ongoing */ |
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rc = flash_stm32_wait_flash_idle(dev); |
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if (rc < 0) { |
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return rc; |
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} |
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/* |
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* If an erase operation in Flash memory also concerns data |
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* in the instruction cache, the user has to ensure that these data |
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* are rewritten before they are accessed during code execution. |
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*/ |
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flush_cache(regs); |
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tmp = regs->CR; |
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page = offset / STM32G0_FLASH_PAGE_SIZE; |
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#if defined(STM32G0_DBANK_SUPPORT) |
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bool swap_enabled = (regs->OPTR & FLASH_OPTR_nSWAP_BANK) == 0; |
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/* big page-nr w/o swap or small page-nr w/ swap indicate bank2 */ |
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if ((page >= STM32G0_PAGES_PER_BANK) != swap_enabled) { |
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page = (page % STM32G0_PAGES_PER_BANK) + STM32G0_BANK2_START_PAGE_NR; |
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tmp |= FLASH_CR_BKER; |
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LOG_DBG("Erase page %d on bank 2", page); |
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} else { |
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page = page % STM32G0_PAGES_PER_BANK; |
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tmp &= ~FLASH_CR_BKER; |
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LOG_DBG("Erase page %d on bank 1", page); |
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} |
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#endif |
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/* Set the PER bit and select the page you wish to erase */ |
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tmp |= FLASH_CR_PER; |
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tmp &= ~FLASH_CR_PNB_Msk; |
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tmp |= ((page << FLASH_CR_PNB_Pos) & FLASH_CR_PNB_Msk); |
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/* Set the STRT bit and write the reg */ |
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tmp |= FLASH_CR_STRT; |
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regs->CR = tmp; |
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/* Wait for the BSY bit */ |
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rc = flash_stm32_wait_flash_idle(dev); |
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regs->CR &= ~FLASH_CR_PER; |
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return rc; |
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} |
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int flash_stm32_block_erase_loop(const struct device *dev, |
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unsigned int offset, |
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unsigned int len) |
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{ |
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unsigned int addr = offset; |
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int rc = 0; |
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for (; addr <= offset + len - 1 ; addr += STM32G0_FLASH_PAGE_SIZE) { |
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rc = erase_page(dev, addr); |
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if (rc < 0) { |
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break; |
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} |
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} |
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return rc; |
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} |
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int flash_stm32_write_range(const struct device *dev, unsigned int offset, |
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const void *data, unsigned int len) |
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{ |
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int i, rc = 0; |
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for (i = 0; i < len; i += 8, offset += 8) { |
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rc = write_dword(dev, offset, ((const uint64_t *) data)[i>>3]); |
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if (rc < 0) { |
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return rc; |
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} |
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} |
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return rc; |
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} |
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/* |
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* The address space is always continuous, even though a subset of G0 SoCs has |
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* two flash banks. |
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* Only the "physical" flash page-NRs are not continuous on those SoCs. |
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* As a result the page numbers used in the zephyr flash api differs |
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* from the "physical" flash page number. |
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* The first is equal to the address offset divided by the page size, while |
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* "physical" pages are numbered starting with 0 on bank1 and 256 on bank2. |
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* As a result only a single homogeneous flash page layout needs to be defined. |
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*/ |
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void flash_stm32_page_layout(const struct device *dev, |
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const struct flash_pages_layout **layout, |
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size_t *layout_size) |
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{ |
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static struct flash_pages_layout stm32g0_flash_layout = { |
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.pages_count = 0, |
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.pages_size = 0, |
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}; |
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ARG_UNUSED(dev); |
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if (stm32g0_flash_layout.pages_count == 0) { |
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stm32g0_flash_layout.pages_count = |
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STM32G0_FLASH_SIZE / STM32G0_FLASH_PAGE_SIZE; |
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stm32g0_flash_layout.pages_size = STM32G0_FLASH_PAGE_SIZE; |
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} |
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*layout = &stm32g0_flash_layout; |
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*layout_size = 1; |
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} |
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/* Override weak function */ |
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int flash_stm32_check_configuration(void) |
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{ |
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#if defined(STM32G0_DBANK_SUPPORT) && (CONFIG_FLASH_SIZE == 256) |
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/* Single bank mode not supported on dual bank SoCs with 256kiB flash */ |
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if ((regs->OPTR & FLASH_OPTR_DUAL_BANK) == 0) { |
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LOG_ERR("Single bank configuration not supported by the driver"); |
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return -ENOTSUP; |
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} |
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#endif |
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return 0; |
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}
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