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206 lines
5.7 KiB
206 lines
5.7 KiB
/* |
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* Copyright (c) 2017 Linaro Limited |
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* Copyright (c) 2017 BayLibre, SAS. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_ |
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#define ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_ |
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \ |
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks) |
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#include <drivers/clock_control.h> |
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#include <drivers/clock_control/stm32_clock_control.h> |
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#endif |
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struct flash_stm32_priv { |
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FLASH_TypeDef *regs; |
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \ |
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks) |
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/* clock subsystem driving this peripheral */ |
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struct stm32_pclken pclken; |
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#endif |
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struct k_sem sem; |
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}; |
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#if DT_PROP(DT_INST(0, soc_nv_flash), write_block_size) |
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#define FLASH_STM32_WRITE_BLOCK_SIZE \ |
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DT_PROP(DT_INST(0, soc_nv_flash), write_block_size) |
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#else |
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#error Flash write block size not available |
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/* Flash Write block size is extracted from device tree */ |
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/* as flash node property 'write-block-size' */ |
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#endif |
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/* Differentiate between arm trust-zone non-secure/secure, and others. */ |
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#if defined(FLASH_NSSR_NSBSY) /* For mcu w. TZ in non-secure mode */ |
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#define FLASH_SECURITY_NS |
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#define FLASH_STM32_SR NSSR |
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#elif defined(FLASH_SECSR_SECBSY) /* For mcu w. TZ in secured mode */ |
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#error Flash is not supported in secure mode |
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#define FLASH_SECURITY_SEC |
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#else |
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#define FLASH_SECURITY_NA /* For series which does not have |
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* secured or non-secured mode |
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*/ |
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#define FLASH_STM32_SR SR |
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#endif |
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#define FLASH_STM32_PRIV(dev) ((struct flash_stm32_priv *)((dev)->data)) |
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#define FLASH_STM32_REGS(dev) (FLASH_STM32_PRIV(dev)->regs) |
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/* Redefintions of flags and masks to harmonize stm32 series: */ |
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#if defined(CONFIG_SOC_SERIES_STM32G0X) |
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#if defined(FLASH_FLAG_BSY2) |
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#define FLASH_STM32_SR_BUSY (FLASH_FLAG_BSY1 | FLASH_FLAG_BSY2); |
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#else |
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#define FLASH_STM32_SR_BUSY (FLASH_SR_BSY1) |
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#endif /* defined(FLASH_FLAG_BSY2) */ |
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#else |
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#define FLASH_STM32_SR_BUSY (FLASH_FLAG_BSY) |
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#endif |
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#if defined(CONFIG_SOC_SERIES_STM32G0X) |
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#define FLASH_STM32_SR_CFGBSY (FLASH_SR_CFGBSY) |
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#elif defined(FLASH_FLAG_CFGBSY) |
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#define FLASH_STM32_SR_CFGBSY (FLASH_FLAG_CFGBSY) |
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#endif |
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#if defined(CONFIG_SOC_SERIES_STM32G0X) |
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/* STM32G0 HAL FLASH_FLAG_x don't represent bit-masks, need FLASH_SR_x instead */ |
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#define FLASH_STM32_SR_OPERR FLASH_SR_OPERR |
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#define FLASH_STM32_SR_PGERR 0 |
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#define FLASH_STM32_SR_PROGERR FLASH_SR_PROGERR |
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#define FLASH_STM32_SR_WRPERR FLASH_SR_WRPERR |
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#define FLASH_STM32_SR_PGAERR FLASH_SR_PGAERR |
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#define FLASH_STM32_SR_SIZERR FLASH_SR_SIZERR |
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#define FLASH_STM32_SR_PGSERR FLASH_SR_PGSERR |
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#define FLASH_STM32_SR_MISERR FLASH_SR_MISERR |
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#define FLASH_STM32_SR_FASTERR FLASH_SR_FASTERR |
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#if defined(FLASH_SR_RDERR) |
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#define FLASH_STM32_SR_RDERR FLASH_SR_RDERR |
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#else |
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#define FLASH_STM32_SR_RDERR 0 |
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#endif |
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#define FLASH_STM32_SR_PGPERR 0 |
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#else /* !defined(CONFIG_SOC_SERIES_STM32G0X) */ |
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#if defined(FLASH_FLAG_OPERR) |
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#define FLASH_STM32_SR_OPERR FLASH_FLAG_OPERR |
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#else |
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#define FLASH_STM32_SR_OPERR 0 |
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#endif |
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#if defined(FLASH_FLAG_PGERR) |
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#define FLASH_STM32_SR_PGERR FLASH_FLAG_PGERR |
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#else |
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#define FLASH_STM32_SR_PGERR 0 |
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#endif |
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#if defined(FLASH_FLAG_PROGERR) |
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#define FLASH_STM32_SR_PROGERR FLASH_FLAG_PROGERR |
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#else |
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#define FLASH_STM32_SR_PROGERR 0 |
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#endif |
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#if defined(FLASH_FLAG_WRPERR) |
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#define FLASH_STM32_SR_WRPERR FLASH_FLAG_WRPERR |
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#else |
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#define FLASH_STM32_SR_WRPERR 0 |
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#endif |
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#if defined(FLASH_FLAG_PGAERR) |
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#define FLASH_STM32_SR_PGAERR FLASH_FLAG_PGAERR |
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#else |
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#define FLASH_STM32_SR_PGAERR 0 |
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#endif |
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#if defined(FLASH_FLAG_SIZERR) |
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#define FLASH_STM32_SR_SIZERR FLASH_FLAG_SIZERR |
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#else |
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#define FLASH_STM32_SR_SIZERR 0 |
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#endif |
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#if defined(FLASH_FLAG_PGSERR) |
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#define FLASH_STM32_SR_PGSERR FLASH_FLAG_PGSERR |
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#else |
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#define FLASH_STM32_SR_PGSERR 0 |
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#endif |
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#if defined(FLASH_FLAG_MISERR) |
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#define FLASH_STM32_SR_MISERR FLASH_FLAG_MISERR |
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#else |
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#define FLASH_STM32_SR_MISERR 0 |
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#endif |
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#if defined(FLASH_FLAG_FASTERR) |
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#define FLASH_STM32_SR_FASTERR FLASH_FLAG_FASTERR |
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#else |
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#define FLASH_STM32_SR_FASTERR 0 |
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#endif |
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#if defined(FLASH_FLAG_RDERR) |
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#define FLASH_STM32_SR_RDERR FLASH_FLAG_RDERR |
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#else |
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#define FLASH_STM32_SR_RDERR 0 |
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#endif |
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#if defined(FLASH_FLAG_PGPERR) |
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#define FLASH_STM32_SR_PGPERR FLASH_FLAG_PGPERR |
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#else |
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#define FLASH_STM32_SR_PGPERR 0 |
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#endif |
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#endif /* !defined(CONFIG_SOC_SERIES_STM32G0X) */ |
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#define FLASH_STM32_SR_ERRORS (FLASH_STM32_SR_OPERR | \ |
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FLASH_STM32_SR_PGERR | \ |
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FLASH_STM32_SR_PROGERR | \ |
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FLASH_STM32_SR_WRPERR | \ |
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FLASH_STM32_SR_PGAERR | \ |
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FLASH_STM32_SR_SIZERR | \ |
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FLASH_STM32_SR_PGSERR | \ |
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FLASH_STM32_SR_MISERR | \ |
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FLASH_STM32_SR_FASTERR | \ |
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FLASH_STM32_SR_RDERR | \ |
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FLASH_STM32_SR_PGPERR) |
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#ifdef CONFIG_FLASH_PAGE_LAYOUT |
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static inline bool flash_stm32_range_exists(const struct device *dev, |
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off_t offset, |
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uint32_t len) |
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{ |
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struct flash_pages_info info; |
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return !(flash_get_page_info_by_offs(dev, offset, &info) || |
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flash_get_page_info_by_offs(dev, offset + len - 1, &info)); |
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} |
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */ |
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bool flash_stm32_valid_range(const struct device *dev, off_t offset, |
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uint32_t len, bool write); |
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int flash_stm32_write_range(const struct device *dev, unsigned int offset, |
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const void *data, unsigned int len); |
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int flash_stm32_block_erase_loop(const struct device *dev, |
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unsigned int offset, |
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unsigned int len); |
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int flash_stm32_wait_flash_idle(const struct device *dev); |
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#ifdef CONFIG_SOC_SERIES_STM32WBX |
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int flash_stm32_check_status(const struct device *dev); |
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#endif /* CONFIG_SOC_SERIES_STM32WBX */ |
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#ifdef CONFIG_FLASH_PAGE_LAYOUT |
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void flash_stm32_page_layout(const struct device *dev, |
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const struct flash_pages_layout **layout, |
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size_t *layout_size); |
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#endif |
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#endif /* ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_ */
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