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ee2b9a4e6d
backport-73945-to-v2.7-branch
backport-78976-to-v3.7-branch
backport-80768-to-v3.7-branch
backport-81533-to-v4.0-branch
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collab-hwm
collab-init
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collab-rust
collab-safety
collab-sdk-0.18-dev
collab-sdk-dev
main
v1.10-branch
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${ noResults }
4 Commits (ee2b9a4e6d68da2d3f94b0de247b91dd244d7a19)
| Author | SHA1 | Message | Date |
|---|---|---|---|
Pieter De Gendt
|
6cfb14c823 |
drivers: reset: Place API into iterable section
Add wrapper DEVICE_API macro to all reset_driver_api instances. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be> |
7 months ago |
Gerard Marull-Paretas
|
1eb683a514 |
device: remove redundant init functions
Remove all init functions that do nothing, and provide a `NULL` to *DEVICE*DEFINE* macros. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> |
2 years ago |
Patryk Duda
|
3cbbcefb12 |
drivers: reset: Add support for reset clear register
To deassert reset in STM32MP1 RCC the driver needs to set the bit in reset clear register. This patch extends existing implementation to support this type of register. Signed-off-by: Patryk Duda <pdk@semihalf.com> |
3 years ago |
|
Patryk Duda
|
d6f8e9ae5b |
drivers: reset: Introduce STM32 reset controller
This driver exposes STM32 RCC reset functionality through reset API. Information about RCC register offset and bit is encoded just like GD32. The first 5 least significant bits contains register bit number. Next 12 bits are used to keep RCC register offset. Remaining bits are unused. Signed-off-by: Patryk Duda <pdk@semihalf.com> |
3 years ago |