zara/zephyr - zephyr - Gitea: Git with a cup of tea

Author	SHA1	Message	Date
Aymeric Aillet	d2e79866ad	drivers: clock: rcar: r8a7795 driver cleanup Remove old unused defines from header Use clang-format to apply coding guideline to r8a7795 driver Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>	1 year ago
Mykola Kvach	5461917952	drivers: clock: rcar: Add r8a779f0 support Add support of r8a779f0 cpg driver. r8a779f0 soc has its own clock tree. Gen4 SoCs common registers addresses have been added in header. Signed-off-by: Mykola Kvach <mykola_kvach@epam.com> Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>	2 years ago
Henrik Brix Andersen	5d5249d85b	drivers: can: unify spelling of CAN Flexible Data-rate abbreviation Unify spelling of CAN Flexible Data-rate abbreviation to "CAN FD" instead of "CAN-FD". The former aligns with the CAN in Automation (CiA) recommendation. Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>	2 years ago
Mykola Kvach	644b38a3b7	drivers: rcar_cpg: do MMIO mapping inside driver Add MMIO mapping for Renesas CPG driver in order to avoid mappings inside mmu_regions.c file. Remove MMU region for Renesas CPG driver. Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>	2 years ago
Mykola Kvach	6f24edf5c8	drivers: rcar_cpg: add generic Renesas functions for get/set rate Add associated tables of clocks and API for working with these tables, from this moment the relationship between clocks and their divider are built. After set rate of some Core clock, driver has to update all in/out rates of all childrens recursively. During get/set rate calls if out rate is unknown, we try to get parent in/out rates and its divider, in case when parent doesn't have valid in/out rates we get parent of parent and so on until we get parent with a valid in or out rates. Add generic Renesas functions for get/set rate of CPG. Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>	2 years ago
Pierre Marzin	1d2752f4ee	drivers: pwm: add Renesas R-Car driver Add R-Car Gen3 PWM driver. Clock diviser is automatically adjusted according to requested period and duty-cycle in order to obtain as much accuracy as possible. Indeed, in order to improve PWM accurancy, the PWM clock has to fit the requested period. So use the given period_cycle to define if the clock as to be adapted. In such case, increase/decrease the clock diviser to adapt the period_cycle and be sure that it fits into the 10 bits counter of the PWM controller. Tested on H3ULCB on pwm0 and pwm4. Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>	3 years ago
Aymeric Aillet	df7ca2a24e	drivers/clock/rcar: Move ASSERT to module clock function ASSERT was failing when `r8a7795_cpg_mssr_start_stop` was called for a "core" clock. This ASSERT statement and "mstpcr" table of registers are only meant to be used when starting or stopping a "module" clock. Moved ASSERT statement to `rcar_cpg_mstp_clock_endisable` as well as "reg" & "bit" calculation. Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>	3 years ago
Aymeric Aillet	14ff2b1f88	drivers: clock: rcar: Deploy a driver for each soc This commit rewrite renesas R-Car clock driver in order to be able to support any new SoC easier. This work is so creating a clock driver per soc alongside a common driver for all reneasas r-car boars. - drivers: create a driver per soc - create a common driver - create a common header used by soc & common driver - create a soc specific driver calling for common driver - dts: use new compatible - use old yaml as common yaml - create a new "child" yaml to define the new compatible field - change compatible in device tree As in Linux, the driver can support both r8a77951 and r8a77950 SoC's so we decided to name the new driver as in Linux with Zephyr prefix : "clock_control_r8a7795_cpg_mssr.c". Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>	3 years ago