Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
remove litex,sys-clock-frequency from litex,clk,
because we already define that in the clock-frequency of cpu0.
This can be accessed via
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Remove address-of operator ('&') when assigning `clock_control_xxx_init`
function pointer in `DEVICE_DT_INST_DEFINE` macro.
This change aims to maintain consistency among the drivers in
`drivers/clock_control`, ensuring that all function pointer assignments
follow the same pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Found via static analysis. Two separate error paths where failing to
check the return code leads to undefined behavior:
1. In `litex_clk_get_phase`, the divider stays set to 0 when
`litex_clk_get_clkout_divider` errors out, which leads to a division
by 0.
2. In `litex_clk_calc_duty_normal`, the `duty` struct is used
uninitialized if `litex_clk_get_duty_cycle` errors out.
In both case, checking the return code and returning early resolves the
issue.
Signed-off-by: François Baldassari <francois@memfault.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.
This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.
There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.
Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.
Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.
Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.
Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.
This makes it possible to have code, independent of CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Refactors all of the clock control drivers to use a shared driver class
initialization priority configuration,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control
drivers separately from other devices. This is similar to other driver
classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
The even lower defaults for STM32 and Arm Beetle are preserved by
SoC-family level overrides.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Some tools consider this as commented code because of the ifdef, so
remove that and fix a coding guideline violation.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit adds LiteX SoC Builder clock control driver for MMCM
module. It gives ability to change frequency, phase and duty cycle
on up to 7 clock outputs.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Pieter De Gendt
Pisit Sawangvonganan
Fin Maaß
Benjamin Cabé
François Baldassari
Gerard Marull-Paretas
Daniel Leung
Nick Ward
Gerard Marull-Paretas
Michal Sieron
Maureen Helm
Anas Nashif
Kumar Gala
Pawel Czarnecki