These registers were hardwired in the platform layer. Move to
devicetree, via a struct interface that looks like the pre-existing
shim layer.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These registers are identical on all platforms, the only difference
being that cAVS 1.5 places them at a different address.
Create a devicetree node to track the register block, and replace the
platform header code with a global API defined once (it works like the
pre-existing shim struct).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Each platform was defining its own shim.h header, with slightly
variant field definitions, for a register block that is almost
completely compatible between versions. This is made worse by the
fact that these represent an API imported fairly early from SOF, the
upstream version of which has since diverged.
Move the existing shim struct into a header ("cavs-shim.h") of its
own, remove a bunch of unused symbols, fill in definitions for some
registers that were left out, correct naming to match the hardware
docs in a few places, make sure all hardware dependencies are source
from devicetree only, and modify existing usage to use the new API
exclusively.
Interestingly this leaves the older shim.h header in place, as it
turns out to contain definitions for a bunch of things that were never
part of the shim register block. Those will be unified in separate
patches.
Finally: note that the existing IPM_CAVS_IDC driver (soon to be
removed from all the intel_adsp soc's) is still using the old API, so
redeclare the minimal subset that it needs for the benefit of the
platforms in transition.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is dead code. It's based on the cAVS "IPC" mechanism to allow
communication to and from the host CPU. But there is no test rig in
the Zephyr tree for the protocol defined. And in fact the only
Zephyr-based user of the IPC mechanism (Sound Open Firmware) has its
own IPC driver and speaks its own protocol with the host kernel. That
driver needs to migrate into Zephyr soon and this legacy bit is just
confusing.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Introduce a new RPMsg with static VRINGs backend. This new backend makes
easy to generate and use IPC instances backed by OpenAMP using the DT.
Each instance is defined in the DT as (for example):
ipc: ipc {
compatible = "zephyr,ipc-openamp-static-vrings";
shm = <&sram_ipc0>;
mboxes = <&mbox 0>, <&mbox 1>;
mbox-names = "tx", "rx";
role = "primary";
status = "okay";
};
It is then possible to register an send data through endpoints using the
IPC service APIs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
* With existence of Adafruit Qt Py boards, and upcoming wireless
Xiao from Seeeduino, define nexus node and peripheral node
labels for use with shields that accept any Xiao format board.
* Adds `&xiao_d`, `&xiao_spi`, `&xiao_i2c` and `&xiao_serial` generic
node labels.
* Add new 'seeed-xioa-header.yaml` to document new nexus node.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
Add a pin control driver for GD32 SoCs using the AFIO model.
Thanks to Gerson Fernando Budke for testing and implementation
suggestions.
Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
1.Putting the PWM_CHANNEL_X, PWM_PRESCALER_CX information
in the description.
2.Use the common definition EC_FREQ.
3.Use the common macro IT8XXX2_DT_ALT_ITEMS_LIST.
4.Stop using DRV_CONFIG, DRV_REG macro.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Users will have to include dt-bindings/spi/spi.h in order to use the
relevant flags fol this property. For instance:
...
duplex = <SPI_HALF_DUPLEX>;
....
By default all SPI device are configured to be full duplex so the
property is optional. This property makes sense only for devices that
can be configured on either modes. Which, in such case, it will need to
use DT_INST_PROP(<instance number>, duplex) macro call to retrieve the
property value. Others can fully ignore it.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add tests for the instance based enum macros DT_INST_ENUM_IDX and
DT_INST_ENUM_IDX_OR.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.
Changes include:
- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
IT8XXX2 uses shared ns16550.c driver which does not provide a power
management callback(pm_action_cb), so create driver to handle
IT8XXX2 specific UART features.
note: pm_action_cb(old name: pm_control_fn)
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
Also prescaler is common to all PWM channels of the same timer.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)
For compatibility reason temporarily keep pwm binding to avoid
breaking boards out of tree.
Block st,prescaler property in lptim binding
as lptim doesn't use this property for now.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This will be used to take a phandle to a FEM device, either a generic
two pin device or an nRF21540. Keep the nRF21540 binding example up to
date.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The way the nRF21540 device is configured makes sense once you
understand it, but it's quite unusual: a single peripheral is
configured with two separate devicetree nodes linked by a phandle.
Since this risks entering "exploding head" territory for beginners, it
deserves a thorough example. Add one to the binding's description.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This is a helper binding for radio front-end modules that have a
two-pin control interface, where one pin is used to turn on an power
amplifier (PA) for TX, and another is used to turn on a low-noise
amplifier (LNA) for RX.
Such hardware is already supported by the Bluetooth subsystem, but via
PA/LNA Kconfig settings. Since this is hardware configuration, it is
better to move this to devicetree instead.
Add a binding that makes it possible to define nodes which contain the
same information, along with a bit of extra information related to the
gain in dB of each amplifier not currently available from Kconfig.
This is similar to the existing binding for the nordic,nrf21540-fem
compatible.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Andrzej Kuros <andrzej.kuros@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This is to support upcoming external radio coexistence implementations,
see binding documentation for more info.
Signed-off-by: Jonathan Rico <jonathan.rico@nordicsemi.no>
add ledc to board dtsi file,
change compatible and device define in pwm driver,
add yaml for board ledc support,
fix missing include for board in gpio include
Signed-off-by: Andrei-Edward Popa <andrei_edward.popa@upb.ro>
Use i2c_hal functions to enable support for
multiple SoCs.
Use DT compat to enable I2C from device
tree configuration
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This joins all clock control handling to same source
by using hal clock functions. It also brings ESP32C3
clock support.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the USB On-The-Go Supplement, Revision 2.0 in the DTS
of the stm32u575 and stm32u585 devices
(not for the stm32U5 serie).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In order to have Espressif SoCs working with
the same uart drivers, all low level functions
are now replaced to hal_espressif HAL calls.
This also changes pinmux, gpio and uart
init order to meet its dependencies.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
STM32WL could be either single core (stm32wlex) or
dual core (stm32wl5/4x).
Make CPU2 prescaler an optional property (while it will
be required if inherited from st,stm32wb-rcc.yaml.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that Kconfig option for STM32 clocks configuration has been
removed, set rcc properties as required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Johann Fischer
HaiLong Yang
Andy Ross
Guillaume Lager
Carlo Caione
Peter Johanson
Gerard Marull-Paretas
Wealian Liao
Ruibin Chang
Tomasz Bursztyka
Gerard Marull-Paretas
David Leach
Tim Lin
Alexandre Bourdiol
Lukas Gehreke
Dino Li
Felipe Neves
Martí Bolívar
Jonathan Rico
Neil Armstrong
Nick Ward
Francois Ramu
Andrei-Edward Popa
Sylvio Alves
Erwan Gouriou