zara/zephyr - zephyr - Gitea: Git with a cup of tea

Author	SHA1	Message	Date
Chris Friedt	f4e07d15d6	sys: util: define bits per byte, nibble, and nibbles per byte Collect some common bit-widths redefined in various locations and put them under sys/util.h . Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>	9 months ago
Yong Cong Sin	52a202309b	zephyr: bulk update to DT_NODE_HAS_STATUS_OKAY Change instances of: DT_NODE_HAS_STATUS(<node_id>, okay) to DT_NODE_HAS_STATUS_OKAY(<node_id>) Signed-off-by: Yong Cong Sin <ycsin@meta.com> Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>	9 months ago
Fin Maaß	de82190e13	drivers: clock_control: litex: remove redundant entry remove litex,sys-clock-frequency from litex,clk, because we already define that in the clock-frequency of cpu0. This can be accessed via CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>	1 year ago
Michal Sieron	72a2ec253e	clock_control: litex: Use register names Use `DT_REG_ADDR_BY_NAME` and `DT_REG_SIZE_BY_NAME` to access register properties from dts. Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>	3 years ago
Michal Sieron	2e9154a418	soc: litex-vexriscv: Rewrite litex_read/write Changes signature so it takes uint32_t instead of pointer to a register. Later `sys_read` and `sys_write` functions are used, which cast given address to volatile pointer anyway. This required changing types of some fields in LiteX GPIO driver and removal of two casts in clock control driver. There was a weird assert from LiteX GPIO driver, which checked whether size of first register in dts was a multiple of 4. It didn't make much sense, so I removed it. Previous dts was describing size of a register in terms of subregisters used. New one uses size of register, so right now it is almost always 4 bytes. Most drivers don't read register size from dts anyway, so only changes had to be made in GPIO and clock control drivers. Both use `litex_read` and `litex_write` to operate on `n`bytes. Now GPIO driver calculates this `n` value in compile time from given number of pins and stores it in `reg_size` field of config struct like before. Registe sizes in clock control driver are hardcoded, because they are tied to LiteX wrapper anyway. This makes it possible to have code, independent of CSR data width. Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>	3 years ago
Pawel Czarnecki	ed6c0103a9	drivers: clock control: Add LiteX clock control driver This commit adds LiteX SoC Builder clock control driver for MMCM module. It gives ability to change frequency, phase and duty cycle on up to 7 clock outputs. Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>	5 years ago