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c8d9f4b701
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collab-hwm
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collab-sdk-0.18-dev
collab-sdk-dev
main
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${ noResults }
3 Commits (c8d9f4b70164974fb4ab4523cb3929c38e6f12f0)
| Author | SHA1 | Message | Date |
|---|---|---|---|
Girisha Dengi
|
36e71c839f |
drivers: clock_control: Agilex5 clock control driver updates
The clock controller/manager registers are updated with the correct divider values by bootloader via hand-off data, so now we can use the clock controller to get the clock value of each peripheral during the run time. Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> |
7 months ago |
Pieter De Gendt
|
c25e31512c |
drivers: clock_control: Place API into iterable section
Add wrapper DEVICE_API macro to all clock_control_driver_api instances. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be> |
7 months ago |
|
Girisha Dengi
|
2ca6ffcd79 |
drivers: clock_control: clock driver for Intel Agilex5 platform
This is Intel's proprietary IP which supply the clock for all the system peripherals. Clock manager is initialized only one time during boot up by FSBL (ATF BL2) based on external user settings. Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> |
2 years ago |