CS hold time parameter is not correct which may cause bus fault
randomly.
System hang during status register reading after flash progromming which
is caused by parameter accessing in XIP mode.
Add dummy delay for READ command according the flash datasheet which is
required for SDR mode.
Use FlexSPI internal divider for clock updating instead of register in
CCM to avoid potential risk caused by flash access during clock updating
procedure.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
Some instances of the FLEXSPI IP permit limiting AHB bus access so that
no memory access requests will straddle a page boundary. Add a property
to manage this setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The ADDRSHIFT bit simply left shifts the address written to IPCR0[SFAR],
(or the address used for AHB access), by 5 bits before sending it to the
attached memory. This bit does not have an effect on the base address
used to access the flash/psram device.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for initializing the FLEXSPI when using a flash attached to
the FLEXSPI for XIP. This option is guarded behind a Kconfig, as
enabling it is dangerous and requires special care be taken by the user
to ensure that the configuration of pins and FLEXSPI settings will not
break support for reading the attached flash, as this will break XIP
support.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use custom initialization priority for FLEXSPI MEMC driver. This may be
needed when the MEMC driver must initialize before a flash driver, and
before another MEMC driver (for an attached device, like PSRAM)
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
When multiple devices are used, the FLEXSPI will place their address
spaces sequentially (based on the chip select port used). Additionally,
each device must use different sections of the FLEXSPI LUT table.
Fix the following calculation issues with multi-device usage:
- correct calculation of LUT sequence indices for AHB commands
- correctly add address and sequence offset when submitting FLEXSPI IP
transfer
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Some instances of the FlexSPI IP support a different clock source being
used for port B of the FlexSPI instance. Add a devicetree property and
driver support to enable configuring this property of the hardware.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.
Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update interface of memc flexspi driver to better handle multiple
devices. Previously, using multiple devices on one FlexSPI bus would
require the user to configure each device to install its command table
(referred to as a LUT table by the driver) at an offset, so that it did
not overlap with other devices on the bus.
This commit changes the interface of the memc flexspi driver to instead
configure the LUT and flash device in one call. This allows the memc
driver to record the port each LUT sequence is used with, so that
future FlexSPI transfer requests can have their LUT offsets adjusted
based on the target port (which will correspond to a target device)
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Check XIP state based on the value of CONFIG_FLASH_BASE_ADDRESS. This
check should be more reliable than the SOC based method currently
used.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add a function to update the flexspi bus clock. This is
needed when write operations are done to the hyperflash.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
The MCUX platform always uses pinctrl, there's no need to keep extra
macrology around pinctrl. Also updated driver's Kconfig options to
`select PINCTRL` (note that some already did).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
HAL API changes in ethernet and pwm
SoC RT595 power management code change
west.yml update
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Update flexspi driver init priority to be the
memc driver init priority. This fixes a bug where
the flexspi flash drivers on i.MX RT platforms were
being initialized before the flexspi memc driver.
Since those flash drivers depend on the flexspi
spi bus controller being initialized, the flash drivers
would fail to initialize and cause runtime failures.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Allow configuration of AHB RX buffer allocation. This allows sections
of the AHB RX buffer to be reserved for specific masters, which can
enhance performance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
memc driver was setup to always assume the flexSPI would be in XIP mode,
and skip init. This is only true for the active flexSPI, which is
typically FlexSPI1. Fix this check to only skip init for FlexSPI1
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit fixes an issue introduced in 5ee9392 where FlexSPI
pinctrl states where applied based on the SoC type.
However multiple FlexSPI instances can be active, some of which
are not pre-configured from ROM.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
- The MX25UM51345G flash is connected to FLEXSPI PortA for
mimxrt595_evk.
- Updated flexspi_mx25um51345g driver to support DTR OPI mode.
- Tested with tests/drivers/flash.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Some SOCs, such as the RT1064 and RT1024, use internal flash and don't
define pinmux settings for the flexspi. Don't check the return code of
pinctrl_apply_state, because the flexspi driver will fail to initialize
when the pin mux settings are simply not required.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enable pinctrl for flexspi driver. Note that when flexspi is being using
in XIP mode, pinctrl settings are not required and will not be applied.
Pinctrl settings are only required when the flexspi device being used is
not the one used for XIP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
flexspi driver should not interact with flash whenever possible, and
should never use flash while in a critical write or erase section.
Move device data to RAM to prevent this read-while-write hazard.
Fixes#44043
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Program flow will behave incorrectly (memory and instruction fetches
return invalid data) if Flexspi is accessed by the Flexspi driver while
being used as XIP memory by the Cortex M7.
Set logging to disabled by when XIP mode is used in the memc and
flexspi drivers, and warn the user if they attempt to enable it.
Fixes#40133
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This enables accessing the hyperflash through the flash api.
Added a feature to memc_mcux_flexspi that waits for flexspi bus to be
quiet.
Signed-off-by: Nicolai Glud <nicolai.glud@prevas.dk>
Updating to the SDK 2.10.0 for select platforms.
west.yml:
- Update to point to the NXP HAL update with SDK 2.10.0 files
- modules/tee/tfm needed to be updated to synchronize the
LPCXPRESSO55S69 platform SDK to version 2.10.0 to be in sync
with Zephyr usage of SDK 2.10.0
drivers/counter/counter_mcux_pit.c:
- underlying SDK 2.10.0 adjusted the setting by -1 so need
to adjust the reported value set by +1
drivers/ethernet/eth_mcux.c:
- SDK2.10 ethernet driver provided an assert test that highlighted
we were using the wrong clock source on various platforms.
drivers/memc/memc_mcux_flexspi.c:
- SDK2.10 added compile time conditional on whether a field was
defined for the flexspi configuration structure.
Signed-off-by: David Leach <david.leach@nxp.com>
This change allows writing to the flash while running in XIP mode,
and enables mcuboot or NVS settings to be used on i.MX RT socs.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Initially the flexspi device only supported a flash driver for
external NOR flash. As the controller supports HyperBus devices,
which can be either volatile or non-volatile, the driver iss moved
to drivers/memc.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Introduces a new flash driver for the FlexSPI peripheral on i.MX RT
SoCs. The hardware provides a flexible sequence engine (LUT) that
supports various types of external devices, including serial NOR flash,
serial NAND flash, HyperBus (HyperFlash/HyperRAM), and FPGAs. It
supports up to four connected devices in single/dual/quad/octal modes
and provides memory-mapped read/write access to these devices through
the AHB bus.
The driver implementation consists of a shared controller for each
FlexSPI peripheral instance, and protocol-specific device drivers for
each external device. The controller provides a private interface for
multiple devices to access the FlexSPI peripheral registers. FlexSPI
devices provide the public flash driver interface to applications or
subsystems like storage or flash file systems; they also provide
protocol-specific LUT sequences to the controller.
Currently the only device type supported is QSPI NOR flash, but other
types like HyperFlash will be added later.
XIP is not yet supported, as this requires additional work to relocate
code to RAM and managing interrupts.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Raymond Lei
Daniel DeGrasse
Jeppe Odgaard
Gerard Marull-Paretas
Yves Vandervennet
Declan Snyder
Mahesh Mahadevan
Pieter De Gendt
Chay Guo
Nicolai Glud
David Leach
Saurabh Jagdhane
Maureen Helm