STM32F439 SoC is an STM32F429 with an integrated crypto/hash processor
providing hardware acceleration for encryption (AES and TDES) and hash
(MD5, SHA-1 and SHA-2).
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Migrate LINKLAYER_PLAT_EnableIRQ and LINKLAYER_PLAT_DisableIRQ
from linklayer_plat.c (hal/stm32 module).
Signed-off-by: Nidhal BEN OTHMEN <nidhal.benothmen@st.com>
Migrate LINKLAYER_PLAT_EnableRadioIT and LINKLAYER_PLAT_DisableRadioIT
from linklayer_plat.c (hal/stm32 module) and adapt it using irq
Zephyr APIs.
Correct casting of irq type between using NVIC APIs or irq Zephyr APIs
Signed-off-by: Nidhal BEN OTHMEN <nidhal.benothmen@st.com>
Increase the link layer thread priority to be more than the BLE CTRL
thread and more than the Zephyr BLE stack threads.
Signed-off-by: Nidhal BEN OTHMEN <nidhal.benothmen@st.com>
Add a warning in the build system if both `CONFIG_PM` and
`STM32_ENABLE_DEBUG_SLEEP_STOP` are enabled at the same time. The first
is likely only enabled if the SoC is intended to be driven into low
power states to save power, while the later prevents the SoC from being
as low power as it can be.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Currently, the soc/stm32/ccm.ld is not handled in
CMAKE_LINKER_GENERATOR.
This commit adds support, making STM32 supportable by
alternative linkers such as AC6 and IAR.
This commit also renames a variable to match all other
LOADADDR symbols.
Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
This change splits eth sram region name definition
and configuration.
In the end the configuration is stored only once
er declared name.
This name shall increase readability and maintainability
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
Generate a proper Cmake warning when signing tool isn't available.
This also allows not to fail in Github CI.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Increase the size of the main stack for BLE applications to avoid
stack overflow on STM32WB0x series. Beacon sample was considered as
a reference for the size increase.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
STM32WB0 series was missed when SoC initialization code was migrated
from SYS_INIT routines to the new soc_early_init_hook method
(c.f. commit c6a03606c2)
Update that series' initialization code to align it with all others.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Moves the LV_DRAW_DMA2D_HAL_INCLUDE to the soc instead of the development
kit since the hal include is the same across all boards using the soc.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Add support for STM32H757 SoC, which shares its design
with STM32H747 with added cryptography peripherals.
Signed-off-by: Grzegorz Runc <g.runc@grinn-global.com>
This reverts commit b33b3b17f7, turns out
it's causing issues in CI all over the place, the condition needs more
thinking.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add a compiler warning when building for an STM32 series MCU with PM
enabled but STM32_ENABLE_DEBUG_SLEEP_STOP=y. That option greatly
increases the power consumption during sleep, which is probably
undesirable when building with PM=y, and it can be activated silently
as a side effect of other options (namely RTT) making it tricky to find
out.
Add a warning to expose the situation.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Wakeup pin indices are 1-based, but `LISTIFY` is 0-based. Consequently, the
last element of the pin-to-register-bit lookup table was never populated.
Signed-off-by: Samuel Coleman <samuel.coleman@rbr-global.com>
check if multiples UART instances with same irq are enabled
at same time then enable shared_interrupt handler.
set the default value of SHARED_IRQ_MAX_NUM_CLIENTS config if
we have more than 2 usarts instances enabled.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Release HSI CLK48 semaphore when going to sleep to allow C2 (M0)
core to start and stop clock as needed while C1 core is not running.
CLK48 is shared between RNG and USB. RNG is needed by M0 during BLE
advertisement. If semaphore is locked, C2 core can start it when it
needs to but not stop it.
Fixes zephyrproject-rtos#69955.
Signed-off-by: Jonny Gellhaar <jonny.gellhaar@prevas.se>
Put the default value for BT_AUTO_PHY_UPDATE and BT_AUTO_DATA_LEN_UPDATE
to "n" at SOC level since they cause "controller busy" due to starting
several parallel BLE procedures during connection by
"perform_auto_initiated_procedures" function. At the moment, ST controller
does not support parallelism, i.e. host should not initiate a new procedure
before previous one is completed.
Disable CONFIG_BT_HCI_ACL_FLOW_CONTROL at SOC level.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Files renaming done to better isolate zephyr related
functions from stm32 hal related functions
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
Make the SMPS_MODE define visible from drivers by moving it to soc.h
This define is for example used by the ADC driver to determine if sampling
should be synchronized with the SMPS clock.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Enables the XSPIM2 rail when using GPIO bank N
Enables the XSPIM1 rail when using GPIO bank O or P
Enables the USBvoltage detector when using the GPIO M
Signed-off-by: Francois Ramu <francois.ramu@st.com>
DBGMCU clock handling was not optimal.
If it exists, enable it before dealing with debug configuration in one
block, then deactivate it after in another block.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Similarly to debug in stop mode, enable debug in sleep mode on H7 series,
as initially described by `STM32_ENABLE_DEBUG_SLEEP_STOP` option.
Not extending it further to other series as I won't be able to test.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
# Conflicts:
# soc/st/stm32/common/soc_config.c
HAL_Enable/DisableDBGStopMode() was one of the last usage of HAL
definitions from Legacy HAL APIs.
Use LL instead to harmonize code across series and remove this dependency.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The STM32WB06 and STM32WB07 SoCs do not support SMPS output current limit.
This makes the LL_PWR_SetSMPSPrechargeLimitCurrent function and all the
LL_PWR_SMPS_PRECH_LIMIT_CUR_xxx defines not visible when one of these SoCs
is selected, resulting in a build failure.
Fix this by only handling SMPS current limit when the feature is available.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
check if two or three I2C instances with same irq are enabled
at same time then enable shared_interrupt handler.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Rather setting the driver default in soc, make it directly at symbol
level rather than soc and clean up redundant `select` occurrences.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Fin Maaß
Georgij Cernysiov
Mathieu Anquetin
Nidhal BEN OTHMEN
Guillaume Gautier
Jordan Yates
Robin Kastberg
Erwan Gouriou
Benjamin Cabé
Alexander Kozhinov
Ali Hozhabri
Mathieu Choplain
Fabian Blatz
Grzegorz Runc
Fabio Baltieri
Fabrice DJIATSA
Samuel Coleman
Jonny Gellhaar
Jamie McCrae
Francois Ramu
Alessandro Manganaro
Yong Cong Sin
Dan Collins
Anas Nashif