Without this, setting a value of 0 leaves the bits unchanged rather than
zeroing them.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
The STM32H730 series has a variant built with SMPS. It uses
`stm32h730xxq.h` header file instead of `stm32h730xx.h`, which has the
SMPS macro defined.
This commit adds the `SOC_STM32H730XXQ` configuration option to allow
the build system include the proper header file. With this change,
boards can enable `CONFIG_POWER_SUPPLY_DIRECT_SMPS` to set up the power
supply for the CPU.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
For the stm32 devices that have a HSI48 clock,
the driver enables it, like any other fixed clock,
if needed and supported by the serie.
For stm32L0, SYSCFG VREFINT is also required.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
STM32h7 pllout frequency calculation overflows. In the
worst case pllsrc_freq can be 50Mhz and plln_mul 512 which will cause
an overflow of the intermediate result which leads to wrong frequency
returned. As no intermediate result can be bigger than 960MHz only the
order of operations is changed.
Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
Rename and factorize clock source bindings accessors by moving them
in common header file stm32_clock_control and remove them from
include/dt-bindings/clock/stm32XY_clock.h files
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Make the LSE driving capability configurable for the STM32 series.
Fixes#44737.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
STM32H7 series offer alias addresses to access some registers that could
be accessed by the M4 core on dual core variants.
For instance RCC_AHB3ENR could be accessed at following offsets:
- 0x0D4: Accessible from both cores
- 0x134: Accessible from C1 (M7) core
- 0x194: Accessible from C2 (M4) core (if any)
For most single core H7 variants, the two first addresses were accessible,
but for some others (stm32h7ax/stm32h7bx), only the 'C1 accessible'
was available.
This fact used to be hidden by the use of LL API to access these registers,
providing the required abstraction (an mainly using the first alias
when possible to simplify implementation).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Set bus binding values using registers offset values.
As a consequence update driver to take this into account
in clock_on and clock_off functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of reading registers query the info on sysclock configuration
from existing configuration symbols.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rework clock start up functions in order to allow configuration
and enabling of individual clocks.
This way, each clock defined with a "okay" status will be enabled
even if not part of the sysclock clock tree.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add STM32_FOO_ENABLED and STM32_FOO_FREQ to STM32 fixed clocks:
HSI, HSE, MSI(S), CSI, LSI, LSE..
Replace STM32_LSE_CLOCK by STM32_LSE_FREQ and when possible
replace by new STM32_LSE_ENABLED when making sense.
Fix STM32_PLL3_FOO_ENABLE to STM32_PLL3_FOO_ENABLED
Additionally, add STM32_PLL_FOO_ENABLED definitions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
PLL3 setting should also be protected CFG_HW_RCC_SEMID.
Move semaphore unlock after we're done with PLL3.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32H7B3 supports max SYSCLK and AHB clock frequencies of 280 MHz,
and max APB frequency of 140 MHz
Signed-off-by: Tomislav Milkovic <tomislav.milkovic95@gmail.com>
STM32H7 has different power supply modes but now Zephyr supports just LDO
and direct SMPS. This commit introduses POWER_SUPPLY_CHOICE configuration
parameter and add support for missed power supply modes.
Signed-off-by: Gennady Kovalev <gik@bigur.com>
Fixes#40730.
Refactors all of the clock control drivers to use a shared driver class
initialization priority configuration,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control
drivers separately from other devices. This is similar to other driver
classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
The even lower defaults for STM32 and Arm Beetle are preserved by
SoC-family level overrides.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Update stm32h7 clock_control driver to make use of macros allowing
dts based configuration in coexistance with existing Kconfig method.
Note: Use of IS_ENABLED is removed as it generates warnings in
checkpatch. This checkpatch behavior needs to be reviewed but may
first require a little clean up of IS_ENABLED macro.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added support for STM32H753XX by adding CONFIG_SOC_STM32H753XX to list
of H7 SoC with maximum 480MHz SYSCLK.
Signed-off-by: Jeremy Wood <jeremy@bcdevices.com>
Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3
is used as a clock source by certain peripherals, e.g. LTDC.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Provide a utility function to compute PLL VCO input range so that it
can be re-used for other PLLs.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Line break on #error directive is confusing github and ending up
breaking syntax highligthing in github UI which makes me nervous
during review.
Convert error message to a one liner.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert clock_control drivers from:
DEVICE_AND_API_INIT -> DEVICE_DT_DEFINE
As part of this we also changed STM32_CLOCK_CONTROL_NAME to be based on
devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
VCO input frequency can be checked and set during compile time.
It unfortunately does not work for output frequency because macros in
HAL are defined together with uint32_t type.
This also fixes wrong check in case of HSI used as PLL source.
Signed-off-by: Jan Pohanka <xhpohanka@gmail.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add HSI divisor support for clock tree configuration.
Removed HSI calibration trimming to comply with
common STM32 implementation and use reset default
configuration instead.
Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
Adds preprocessor clock feasibility check to avoid setting
too high clocks to SYSCLK,AHB,APBx buses.
Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
matches with the desired clock configuration by
the M7 core.
Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
Fixed wrong usage of assertions.
Assertions should check that the value is in range and
not out of range.
Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
Armin Brauns
Chen Xingyu
Erwan Gouriou
Francois Ramu
Georgij Cernysiov
Guillaume Gautier
Benjamin Bigler
Aurelien Jarno
Gerard Marull-Paretas
Benedikt Schmidt
Nazar Kazakov
Tomislav Milkovic
Mikkel Jakobsen
Manojkumar Subramaniam
Gennady Kovalev
Maureen Helm
Oliver Yang
Jeremy Wood
Gerard Marull-Paretas
Kumar Gala
Martin Jäger
Alexander Kozhinov
Jan Pohanka
Tomasz Bursztyka
Jeremy LOCHE