Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
First pads are being configured for use by the FPGA.
Then CPU loads usbserial bitstream.
Finally it reenables clocks, sets up USB PID and waits for device to
enumerate.
Also disable software resets in used clocks.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This adds driver for EOS_S3 SoC FPGA.
Signed-off-by: Mateusz Sierszulski <msierszulski@internships.antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Pieter De Gendt
Pisit Sawangvonganan
Gerard Marull-Paretas
Fabio Baltieri
Michal Sieron
Gerard Marull-Paretas
Mateusz Sierszulski
Mateusz Sierszulski