Tree:
697d0f845d
backport-73945-to-v2.7-branch
backport-78976-to-v3.7-branch
backport-80768-to-v3.7-branch
backport-81533-to-v4.0-branch
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backport-92779-to-v3.7-branch
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collab-hwm
collab-init
collab-mesh-subnet
collab-rust
collab-safety
collab-sdk-0.18-dev
collab-sdk-dev
main
v1.10-branch
v1.11-branch
v1.12-branch
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v1.14-branch
v1.5-branch
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zephyr-v1.12.0
zephyr-v1.13.0
zephyr-v1.14.0
zephyr-v1.14.1
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${ noResults }
4 Commits (697d0f845d26692929ea3cb15a968c64f6925856)
| Author | SHA1 | Message | Date |
|---|---|---|---|
Robert Hancock
|
f8b4a04186 |
drivers: mdio: mdio_xilinx_axienet: Add access timeouts
Previously if the MDIO access failed to complete, the driver could enter an infinite busy loop. Add timeouts to fail the operation if the hardware fails to respond within a reasonable time. Signed-off-by: Robert Hancock <robert.hancock@calian.com> |
2 weeks ago |
|
Robert Hancock
|
e673f1851f |
drivers: mdio: mdio_xilinx_axienet: Reduce log levels
Reduce log messages which can be triggered noisily by some PHY drivers to debug level. Signed-off-by: Robert Hancock <robert.hancock@calian.com> |
2 weeks ago |
Pieter De Gendt
|
7b1d748e8b |
drivers: Wrap device driver APIs using DEVICE_API macro
Put the device APIs in their respective linker sections with the DEVICE_API wrapper macro. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be> |
2 months ago |
Eric Ackermann
|
4342d7108b |
drivers: ethernet: Add Xilinx AXI Enet driver
The Xilinx AXI Ethernet subsystem is commonly found in FPGA designs. This patch adds a driver and device tree bindings for the Ethernet MAC core and its MDIO controller. The driver was tested on a RISC-V softcore in an FPGA design, with an RGMII phy and Ethernet subsystem version 7.2 Rev. 14. Device tree bindings match the device tree generated by Vitis hsi. Note that Vitis generates one of the two included compatible strings depending on version. Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de> |
4 months ago |