zephyr

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Author	SHA1	Message	Date
Henrik Lindblom	6a3309a9e4	cache: stm32: add cortex-m33 peripheral driver STM32 Cortex-M33, such as the L5/H5/U5 series, have a cache peripheral for instruction and data caches, which are not present in the C-M33 architecture spec. The driver defaults to direct mapped cache as it uses less power than the alternative set associative mapping [1]. This has also been the default in stm32 soc initialization code for chips that have the ICACHE peripheral, which makes it the safest choice for backward compatibility. The exception to the rule is STM32L5, which has the n-way cache mode selected in SOC code. [1]: https://en.wikipedia.org/wiki/Cache_placement_policies Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>	3 months ago

Author

SHA1

Message

Date

Henrik Lindblom

6a3309a9e4

cache: stm32: add cortex-m33 peripheral driver

STM32 Cortex-M33, such as the L5/H5/U5 series, have a cache peripheral for
instruction and data caches, which are not present in the C-M33
architecture spec.

The driver defaults to direct mapped cache as it uses less power than the
alternative set associative mapping [1]. This has also been the default in
stm32 soc initialization code for chips that have the ICACHE peripheral,
which makes it the safest choice for backward compatibility. The exception
to the rule is STM32L5, which has the n-way cache mode selected in SOC
code.

[1]: https://en.wikipedia.org/wiki/Cache_placement_policies

Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>

3 months ago

1 Commits (697d0f845d26692929ea3cb15a968c64f6925856)