Remove address-of operator ('&') when assigning `init_fn`
function pointer in `DEVICE_DT_INST_DEFINE` macro.
This change aims to maintain consistency among the drivers in
`drivers/spi`, ensuring that all function pointer assignments
follow the same pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Subghzspi instances cannot have any pinctrl configs. This causes a
failure of the power management suspend and resume operations for the
subghzspi instance because no "default" pinctrl is found.
Fix that by skipping the pinctrl parts on subghzspi instances.
At the same time fix a copy and paste in the suspend error message.
Fixes: b567a7db83
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add runtime power management suppor to the STM32 SPI driver. This allows
the driver to be suspended when not in use, and as a stop effect removes
the need to suspend/resume around each transition to stop mode.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Keep the SPI enabled when performing multiple transaction with
SPI_HOLD_ON_CS.
In such case, the end of transaction is marked by application calling
spi_release.
Signed-off-by: Michele Sardo <msmttchr@gmail.com>
Supurious interrupts can be generated when the SPI device
is disabled. Ignore them within the SPI IRQ handler.
Co-authored-by: Georgij Cernysiov <geo.cgv@gmail.com>
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Allow to use H7 SPI FIFO to improve performance.
SPI FIFO usage can be enabled/disabled from devicetree.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Set the transfer size in SPI H7 and check EOT instead of TXC
to be sure the transaction has finished. This is required to
enable the use of the SPI FIFO, as otherwise SPI seems to
operate in "continuous mode", which produces several SCK cycles
after the last frame has been sent/received. More details in the PR.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Extend the workaround for the unreliable SPI busy flag
to all F7 and L4 devices, which are affected by the same
erratum.
Fixes #67739
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Master Inter-Data Idleness and Master SS Idleness
can configure with STM32 low level spi driver apis.
Signed-off-by: Mustafa Abdullah Kus <mustafa.kus@sparsetechnology.com>
This reverts commit bffa0c6bdd.
This FIFO implementation causes a regression by which the SPI
peripheral generates several spurious SCK cyles after the last
data has been sent.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Simplify and clarify spi_stm32_shift_m by splitting it in
3 smaller functions with clear names.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
In H7, TXP indicates when its FIFO has room for, at least, one
packet. Thus, rename ll_func_tx_is_empty as ll_func_tx_is_not_full,
to be consistent in all platforms.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Avoind calling startMasterTransfer multiple times in a
transaction by moving it to the transceive() function.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
For some STM32 MCUs the busy flag of SPI is unreliable. This is a known
issue of the device and described in the device errata.
As a fix implement a configurable timeout which ensures that a call
to spi_transceive will eventually return.
Fixes#64927
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Modify STM32H7 SPI driver so that it updates the rx/tx
pointers correctly (depending on the frame size) when DMA
is enabled. Also, make the dummy rx/tx buffer cache-coherent.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
The way of setting a nocache region in devicetree has changed.
Adapt the H7 SPI driver to this new circumstance.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Drivers should only log extra information during initialization if
debug logging is enabled. Otherwise it always clutters the console
when not required.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
This is the final step in making the `zephyr,memory-attr` property
actually useful.
The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.
With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.
The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).
For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_VOLATILE |
DT_MEM_NON_CACHEABLE |
DT_MEM_OOO )>;
};
The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-region = "NOCACHE_REGION";
zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
};
See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).
The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
DT_MEM_SW_ALLOCATABLE )>;
};
Or maybe we can leverage the property to specify some alignment
requirements for the region:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_CACHEABLE |
DT_MEM_SW_ALIGN(32) )>;
};
The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).
When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`
Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
When doing a TX-only SPI operation, the RX not empty flag will never get
set, thus this will just hang forever.
Found/tested on STM32L462 trying to drive some WS2812 RGB LEDs.
Signed-off-by: David Lamparter <equinox@diac24.net>
CONFIG_NOCACHE_MEMORY is a valid way of declaring buffers in
nocache regions. Consider them valid in the stm32 SPI driver
nocache check. Also, don't check NULL buffers as the SPI
interface states that such buffers will result in sending
zeroes.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
DMA only works with non-cached memory regions in H7. Check them
and return an error if they don't match this condition.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Replace the timeout for a SPI transceive in slave mode for STM32 DMA
operations with a K_FOREVER. Being an SPI slave means we do not
know when the transaction will start, hence it does not make sense
to have a timeout in such a case.
This will resolve issue #60000.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Make use of positive status values in the DMA callback to pass
info to the DMA client after a successful DMA operation.
A completed DMA transfer uses the status 0 while a reached
water mark uses the status 1.
Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
Add spi_cs_is_gpio(_dt) helpers to check whether SPI CS is controlled by
GPIO or not. This both improves code readability and isolates SPI
internals.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
As of today it is not possible to use SPI dt-spec macros in C++,
something known and documented. The main reason is because `cs` property
is initialized using a compound literal, something not supported in C++.
This PR takes another approach, that is to not make `cs` a pointer but a
struct member. This way, we can perform a regular initialization, at the
cost of using extra memory for unused delay/pin/flags if `cs` is not
used.
Fixes#56572
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Return correctly the number of received bytes for a
spi_transceive on a STM32 SPI slave.
Fixes#52216
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is the adaptation of the stm32 SPI driver with DMA
transfer for the stm32u5 soc.
Use the DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
also valid for the stm32U5 serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Adds a new spi_transcieve_cb API which enables asynchronous
SPI transactions with callback notification.
The exist spi_transcieve_async API remains and uses the new
spi_transcieve_cb API to provide a k_poll_signal notifier.
The driver API changes to provide a callback and userdata
parameter to async transcieve. All drivers in the tree
have been updated to the change.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
In the continuation of the previous commit, replace _OPT_ by _DOMAIN_
in macros relating to this feature.
hen, adapt drivers and tests to this new wording.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of using or'ed list of Kconfig options listing the compatible
series with what can be called "stm32h7 variant", use the matching
compatible information.
This will prevent to update the driver next time that a compatible series
is ported into zephyr.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support for an alternate clock. If available,
alternate clock is enabled and used to get the
device clock rate.
Fixes#41650
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
When using DMA to transfer over the spi, the spi_stm32_cs_control
is done after enabling the SPI. The same sequence applies
in the transceive_dma function as in transceive function
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Stop using redundant DEV_DATA/DEV_CFG macros and use dev->data
and dev->config instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
the stm32 spi drivers now takes the DTS frame_format property
from the include/ drivers/spi.h
It will be possible to select the Motorola (default)
or TI from the DTS entry of the device,
when soc supports it, else a run time error is raised.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Subghzspi instances cannot have any pinctrl configs,
they are blacklisted by the dts binding. This caused an
initialization failure of the spi_ll_stm32 driver for
subghzspi instance because no "default" pinctrl was found.
This commit solves the problem by skipping the pinctrl setup
for subghzpi devices. The use_subghzpi_nss property is used
to identify a subghzspi device, as this is a required boolean
property only available in the subghzspi binding this is a
perfect indicator for such instances.
Signed-off-by: Alexander Mihajlovic <a@abxy.se>
Luis Ubieda
Pisit Sawangvonganan
Abderrahmane Jarmouni
Aurelien Jarno
Guillaume Gautier
Michele Sardo
Daniel Gaston Ochoa
Benedikt Schmidt
Mustafa Abdullah Kus
Gustavo Silva
Georgij Cernysiov
Hein Wessels
Carlo Caione
Erwan Gouriou
David Lamparter
Cyril Fougeray
Gerard Marull-Paretas
Rami Saad
Francois Ramu
Tom Burdick
Henrik Brix Andersen
Erwan Gouriou
Alexander Mihajlovic