zara/zephyr - zephyr - Gitea: Git with a cup of tea

Author	SHA1	Message	Date
Huaqi Fang	a7f9ebe9d5	driver: interrupt_controller: intc_clic: support 32 and 64 bit riscv cpu This patch is used to provide clic(eclic) in 64 bit riscv cpu support, since in 64 bit riscv cpu, the clic irq table entry is also 64 bit, so we need to use ld/sd to do irq entry load and store Signed-off-by: Huaqi Fang <578567190@qq.com>	3 months ago
Jimmy Zheng	9349d54074	driver: interrupt_controller: intc_clic: rework to standard CLIC driver Rework intc_clic to standard CLIC driver with Nuclei ECLIC extention. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>	3 months ago
Jimmy Zheng	21f0ee0383	driver: interrupt_controller: rename intc_nuclei_eclic to intc_clic Rename intc_nuclei_eclic to intc_clic, and separate CLIC register definitions into intc_clic.h. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>	3 months ago
Jimmy Zheng	a7096fac7d	drivers: interrupt_controller: nuclei_eclic: always use clic common entry When CONFIG_RISCV_VECTORED_MODE is disabled, CLIC claims interrupts using CSR 'mnxti' and handles all pending interrupts before exiting the ISR. When CONFIG_RISCV_VECTORED_MODE is enabled, all interrupts use vector mode and are claimed automatically. The RISC-V common ISR is used for interrupts hooked into SW ISR table, but it only handle one pending interrupt per ISR. This commit enhances CLIC to set vector mode for direct ISRs only and use the CLIC common entry for regular ISRs to handles multiple pending interrupts in an ISR. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>	11 months ago
Jimmy Zheng	89250adea6	drivers: interrupt_controller: intc_nuclei_eclic: fixed $ra polluted Both $ra and $t2 are caller-saved registers and may be modified in ISR callback. Save $ra to stack to follow the calling convention. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>	12 months ago
Greter Raffael	08a2ca5b9b	riscv: irq: Correct interrupt handling in clic non-vectored mode According to the clic specification (https://github.com/riscv/riscv-fast-interrupt), the mnxti register has be written, in order to clear the pending bit for non-vectored interrupts. For vectored interrupts, this is automatically done. From the spec: "If the pending interrupt is edge-triggered, hardware will automatically clear the corresponding pending bit when the CSR instruction that accesses xnxti includes a write." I added a kconfig `RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING` to allow custom irq handling. If enabled, `__soc_handle_all_irqs` has to be implemented. For clic, non-vectored mode, I added a `__soc_handle_all_irqs`, that handles the pending interrupts according to the pseudo code in the spec. Signed-off-by: Greter Raffael <rgreter@baumer.com>	1 year ago