In hal_stm32 commit "update stm32h7rs to cube version V1.2.0"
e5eba65b76
the constants FLASH_OPTKEY1/2 for the STM32H7RS have been renamed to
FLASH_OPT_KEY1/2. For backward compatibility, 2 defines have been added
to Legacy/stm32_hal_legacy.h, so that FLASH_OPTKEYx is an alias for
FLASH_OPT_KEYx.
However, in Zephyr's STM32 flash driver, the alias is defined the other
way around since 5dc537389a, which leads to
Twister build failures, for example
https://github.com/zephyrproject-rtos/zephyr/actions/runs/14927867714/job/41936931524#step:12:1335
To fix the build issue, we can simply remove that alias in Zephyr, since
it is no longer needed.
Signed-off-by: Titouan Christophe <titouan.christophe@mind.be>
Move the flash_stm32_write_protection and
flash_stm32_option_bytes_lock functions to a common
file for stm32 devices including stm32h7
Signed-off-by: Francois Ramu <francois.ramu@st.com>
-The stm32wba6x has Dual Bank memory. Change the flash driver
to support this OPTion given by presence of the
DUAL_BANK bit (21) in the FLASH_OPTR register.
-Flash erase with 2 banks: Add the control of the BKER
bit of the FLASH_NSCR1 to select BANK1 or 2 of
the internal flash depending
on the page number >127 for BANK2
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Use uint64_t instead of uint32_t for the FLASH_STM32_EX_OP_SECTOR_WP
extended operation.
Some chips have two banks, more than 16 sectors each e.g. stm32h7a3xx
chips, so more than 32 bits are required.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Add two new flash extended operations for reading and writing STM32
option bytes from the application code.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Place the flash_stm32_sem_take and flash_stm32_sem_give
function to header file for common to use in any flash driver
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the support of the stm32h7rs serie to the flash stm32h7 driver
Remap Flash registers to the stm32h7rs serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
For the flash driver, the base address is the MCU internal flash
address (usually 0x8000000). This PR gets the that address
from the device tree node "st,stm32-nv-flash"
instead of relying on the CONFIG_FLASH_BASE_ADDRESS
which might differ when building for another flash memory.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
STM32L5 have a write block size of 8, but STM32U5 and STM32H5 have a
write block size of 16. Use write-block-size from the device tree
instead of hardcoding this value when validating the range of write
operations.
Fixes#60724
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
This patch makes possible to choose custom byte which should be used
to enable non-permanent readout protection (RDP1). Actually, any byte
except 0xAA and 0xCC (which are used by RDP0 and RDP2 respectively)
can be used to enable RDP1 but in multi-image environment, some other
image could check if RDP1 is enabled by comparing it to some hardcoded
value.
If property is not defined, 0x55 will be used to enable RDP1. The
default value comes from STM32 HAL.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This patch adds flash readout protection support for STM32F4 devices
family. These devices can enable protection on entire flash content.
Readout protection functionality was exposed as vendor extended
operation. To change readout protection state, caller should provide a
structure which describes desired RDP state.
Enabling readout protection permanently or disabling readout protection
(changing from level 1 to level 0) is guarded by
CONFIG_FLASH_STM32_READOUT_PROTECTION_PERMANENT_ALLOW and
CONFIG_FLASH_STM32_READOUT_PROTECTION_DISABLE_ALLOW respectively.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This patch adds sector write protection support for STM32F4 devices
family. These devices can protect flash content with sector precision.
Write protection functionality was exposed as vendor extended operation.
To change write protection state, caller should provide mask of enabled
and disabled sectors.
Function responsible for locking/unlocking option bytes was implemented
for all STM32 devices supported by this driver.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Introduce the stm32h5 serie to the the existing flash driver
It is based on the stm32l5 model.
Add a function to check if the flash is in dual
or single bank mode.
Some stm32 devices can map 2 or 1 flash banks.
Adapt the FLASH register names for the stm32h5 mcu.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
redefine all the stm32 flash register bit Name from
FLASH_NSCR_xxx to FLASH_STM32_FLASH_NSCR_xxx
in all the zephyr drivers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds the stm32U5 soc family to the flash driver
The flash controller has particular register names in the Non-Secure
area to be adapted for the driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Some series (namely g0, u5, wb, wl, ?) use CFGBSY to indicate
that FLASH_CR is not ready to be modfied.
This commit adds this flag additionally to other the flash busy flags,
in flash_stm32_wait_flash_idle such that the driver waits before
trying to modify PG, PNB[6:0], PER, and MER bits in FLASH_CR.
Additionally, dual bank variants of STM32G0 have a seperarate BSY2 flag
for flash bank two.
Until now this was not yet checked in flash_stm32_wait_flash_idle.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
In STM32G0 HAL FLASH_FLAG_xxx defines don't follow the pattern of
other Series to simply redefine the FLASH_SR_xxx Msk.
Instead an ID for the SR reg and the position of the Error flag
are defined.
As a result error checking in flash_stm32_check_status was not working
until this fix on stm32g0 series.
In order to avoid complexity in the driver, the ifdef-ery of the flags
was moved to the header file.
Other series except g0 use FLASH_FLAG_xxx defines, because those
are valid for both cores in dual core(wl) and in secure/non-secure
targets(l5,u5).
FLASH_STM32_SR_ERRORS mask is introduced to check for any active error
in the SR.
The flags for SIZERR, MISERR, FASTERR are newly introduced.
the latter two are only required once fast programming is used,
which is not yet the case for any series.
The FLASH_SR_OPTVERR flag (option validity flag) is also present
in the SR, but is not added.
Also ecc errors are generally not checked, but these are in a different
register.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
An attempt to simplify the ifdef-ery around FLASH_SR is made.
Define Registers and flags in the header file instead of including
several individual operations in the driver.
FLASH_FLAG_BSY is not only defined for STM32L5, but also other series.
Therefore use this flag instead of FLASH_SR_BSY.
Only the g0 series definition is not valid in our context,
therefore use FLASH_SR_BSY1 instead.
No functional changes, only refactoring.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit fixes missing pclken member if used for h7 series.
Additionally to the check if instance 0 of compatible
st_stm32_flash_controller has defined a clock,
this needs to be checked for compatible st_stm32h7_flash_controller.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Fixes#29831: Implements flash driver for stm32h7 devices.
The driver is independant from the other stm32 families (flash_stm32.c),
only the header interface is (mainly) common.
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
Fixes#29831: Implements flash driver for stm32h7 devices.
The driver is independant from the other stm32 families (flash_stm32.c),
only the header interface is (mainly) common.
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add support for STM32L0X using the generic STM32 backend. This is
quite a significant change since the L0 series uses a slightly
different flash controller. Refactor the generic backend to better
support different block sizes and the L0's register interface.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Remove soc/arm/st_stm32/stm32YY/flash_registers.h files.
Change register accesses in stm32 flash drivers to use FLASH_TypeDef
from modules/hal/stm32/stm32cube/stm32YYxx/soc/stm32xxxxxx.h.
Fixes#16235
Signed-off-by: Sarvesh Patkar <psarvesh314@gmail.com>
The build infrastructure should not be adding the drivers subdirectory
to the include path. Fix the legacy uses that depended on that
addition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add flash support for STM32G0X SoC series.
Signed-off-by: Philippe Retornaz <philippe@shapescale.com
Signed-off-by: Francois Ramu <francois.ramu@st.com>
move clock_control.h to drivers/clock_control.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A common driver is shared between stm32 chips, which was not the case
for stm32f3 series. As a consequence stm32f3 was not maintained
equally and was missing features such as flash layout or dts based
configuration.
Besides, drivers had some flows such as wrong bus clock and
missing HSI clock activation which lead to issues on boards not
using HSI as main clock.
As a consequence this commit moves stm32f3 series flash driver to
common stm32 flash drivers.
Fixes#4197
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This patch adds a flash driver for the STM32F7x series, inspired from
the STM32F4x one. It has been tested on the STM32F723, but should also
work on other SoCs of the family.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add the STM32F0 Embedded Flash support in the flash_stm32 driver
interface.
The STM32F0 has a particularity or use the HSI as clock source
for the flash controller interface, so this clock must be
enabled directly in the case HSE or another clock is used by
the system clock.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add flash page layout support for STM32F4 SoCs.
This almost eliminates the need for flash_map.h, except for
STM32F4X_SECTOR_MASK, so delete the file and move the define into the
F4 implementation, to keep things simple.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
This is a prep work commit for adding flash page layout support.
The internal flash APIs for STM32 on L4 and F4 are a bit
inconsistent. Some routines take a pointer to the private data, others
don't. Those that do take it as a last argument instead of a
first. Additionally, some APIs are declared in flash_stm32.h that
aren't ever used by the family-specific files.
Clean this up by making everything take a struct device*, and marking
routines static in the common driver code when possible.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
L4 write access requires 64 bits alignment
while L4 read access does not require any alignment.
To support specific check according to read/write,erase
a parameter is added to stm32_valid_range.
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
The STM32L4x SoCs embeds a slightly different embedded flash controller
from the STM32F4x SoCs.
This particular controller has the following properties :
- Up to 2 512KiB banks divided in 2KiB pages
- Flash can be accessed in any sizes
- Flash must be written in 64bit aligned 64bit double-words
The drivers/flash/flash_stm32f4x.c is refactored into a new common
drivers/flash/flash_stm32.c and drivers/flash/flash_stm32l4x.c is
created with the STM32L4x specific functions.
To ease the refactoring and keep common functions, the STM32L4x flash
headers are slightly modified to match the hardware reference naming
and solve compilation issues.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Titouan Christophe
Francois Ramu
Dawid Niedzwiecki
Fabio Baltieri
Benedikt Schmidt
Florian Vaussard
Guillaume Gautier
Patryk Duda
Gerard Marull-Paretas
Nazar Kazakov
Thomas Stranger
Krishna Mohan Dani
Nicolas VINCENT
Anas Nashif
Tomasz Bursztyka
Andreas Sandberg
Kumar Gala
Sarvesh Patkar
Peter Bigot
Feng Cheng
Richard Osterloh
Erwan Gouriou
Aurelien Jarno
Flavio Ceolin
Neil Armstrong
Marti Bolivar
Michel Jaouen