zephyr

118395 Commits

85 Branches

204 Tags

1.8 GiB

Tree: 1ff7d1c638

Commit Graph

Author	SHA1	Message	Date
Andy Ross	fe5c11db05	boards/mediatek: Add mt8196_adsp Add Zephyr support for the Audio DSP on the MT8196 SOC. This is a very similar device to previous designs. Most of this patch is just DTS. The biggest delta is the more complicated second level interrupt controller, though it is still able to be represented using some vaguely clever DTS config over the older intc_mtk_adsp driver. Also the memory layout is slightly different, requiring a little indirection to set the initial boot stack address and log output buffer. And the timer "irq_ack" register bits moved. Signed-off-by: Andy Ross <andyross@google.com>	7 months ago
Andy Ross	e0c56f1998	drivers/timer: MediaTek audio DSP timer device These devices have a somewhat odd hybrid design, with a free-running 64 bit up counter but no comparator. Instead interrupts are triggered by (one of an array of) 32 bit down counters with reset (a-la SysTick, but without the 24 bit precision issues). The combination actually results in a fairly simple driver as we can skip the comparator rounding math. Signed-off-by: Andy Ross <andyross@google.com>	1 year ago

Author

SHA1

Message

Date

Andy Ross

fe5c11db05

boards/mediatek: Add mt8196_adsp

Add Zephyr support for the Audio DSP on the MT8196 SOC.  This is a
very similar device to previous designs.  Most of this patch is just
DTS.

The biggest delta is the more complicated second level interrupt
controller, though it is still able to be represented using some
vaguely clever DTS config over the older intc_mtk_adsp driver.

Also the memory layout is slightly different, requiring a little
indirection to set the initial boot stack address and log output
buffer.  And the timer "irq_ack" register bits moved.

Signed-off-by: Andy Ross <andyross@google.com>

7 months ago

Andy Ross

e0c56f1998

drivers/timer: MediaTek audio DSP timer device

These devices have a somewhat odd hybrid design, with a free-running
64 bit up counter but no comparator.  Instead interrupts are triggered
by (one of an array of) 32 bit down counters with reset (a-la SysTick,
but without the 24 bit precision issues).  The combination actually
results in a fairly simple driver as we can skip the comparator
rounding math.

Signed-off-by: Andy Ross <andyross@google.com>

1 year ago

2 Commits (1ff7d1c6388a6390f0288628f951cefa6e5d9ff1)