zephyr

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Author	SHA1	Message	Date
Immo Birnbaum	fef27d8231	drivers: gpio: xlnx_ps: switch driver over to DEVICE_MMIO mapping Set up a named device MMIO memory mapping in the GPIO controller's parent device, map the virtual memory in the init function of the parent device. Once the controller's register space has been successfully mapped, propagate the mapped virtual address to all child (= GPIO bank) devices. While it is possible to add a named mapping to every single GPIO bank device and initialize it in the respective bank device's init function, this would result in multiple virtual address mappings all pointing to the same 4k of physical memory. I assume that, although all those mappings having the same attri- butes, such a setup is at least discouraged. Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>	7 months ago
Kumar Gala	5851a7b7de	drivers: gpio: xlnx_ps: Fix compiler warning Recent change to constify struct devices pointers introduced a compile warning in gpio_xlnx_ps driver. Update driver to fix a case that got missed in the constification that fixes the warning. Signed-off-by: Kumar Gala <galak@kernel.org>	3 years ago
Immo Birnbaum	ca33905248	drivers: gpio: Xilinx PS MIO / EMIO GPIO driver Driver implementation for the Xilinx Processor System MIO / EMIO GPIO controller as contained in the Zynq-7000 and ZynqMP (UltraScale) SoCs. The driver is split up into source and header for a parent controller device and source and header for 1..n child GPIO pin bank devices. The parent device driver takes care of IRQ handling, the GPIO pin bank driver provides pin / bank access according to the API defined by the GPIO subsystem. More than one device for this type of GPIO controller is required as it provides access to a number of GPIO pins well in excess of the 32 pins addressable by the current GPIO API (whereever parameters or return values come in the form of a bit mask): - Zynq-7000: 54 MIO GPIO pins, 64 EMIO GPIO pins in 4 banks. - ZynqMP: 78 MIO GPIO pins, 96 EMIO GPIO pins in 6 banks. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>	3 years ago

Author

SHA1

Message

Date

Immo Birnbaum

fef27d8231

drivers: gpio: xlnx_ps: switch driver over to DEVICE_MMIO mapping

Set up a named device MMIO memory mapping in the GPIO controller's
parent device, map the virtual memory in the init function of the
parent device.

Once the controller's register space has been successfully mapped,
propagate the mapped virtual address to all child (= GPIO bank)
devices. While it is possible to add a named mapping to every
single GPIO bank device and initialize it in the respective bank
device's init function, this would result in multiple virtual
address mappings all pointing to the same 4k of physical memory.
I assume that, although all those mappings having the same attri-
butes, such a setup is at least discouraged.

Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>

7 months ago

Kumar Gala

5851a7b7de

drivers: gpio: xlnx_ps: Fix compiler warning

Recent change to constify struct devices pointers introduced a
compile warning in gpio_xlnx_ps driver.  Update driver to fix a
case that got missed in the constification that fixes the warning.

Signed-off-by: Kumar Gala <galak@kernel.org>

3 years ago

Immo Birnbaum

ca33905248

drivers: gpio: Xilinx PS MIO / EMIO GPIO driver

Driver implementation for the Xilinx Processor System MIO / EMIO GPIO
controller as contained in the Zynq-7000 and ZynqMP (UltraScale) SoCs.

The driver is split up into source and header for a parent controller
device and source and header for 1..n child GPIO pin bank devices.
The parent device driver takes care of IRQ handling, the GPIO pin bank
driver provides pin / bank access according to the API defined by the
GPIO subsystem.

More than one device for this type of GPIO controller is required as
it provides access to a number of GPIO pins well in excess of the 32
pins addressable by the current GPIO API (whereever parameters or
return values come in the form of a bit mask):

- Zynq-7000: 54 MIO GPIO pins, 64 EMIO GPIO pins in 4 banks.
- ZynqMP:    78 MIO GPIO pins, 96 EMIO GPIO pins in 6 banks.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>

3 years ago

3 Commits (main)