For the flash driver, the base address is the MCU internal flash
address (usually 0x8000000). This PR gets the that address
from the device tree node "st,stm32-nv-flash"
instead of relying on the CONFIG_FLASH_BASE_ADDRESS
which might differ when building for another flash memory.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Most implementations have the same logic, with only a different write
block size. Now that we are using write-block-size from the device tree,
it is possible to use a default implementation that can be overridden if
necessary.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
On stm32g0, stm32g4, stm32l4, stm32l5, stm32u5,
and stm32wbx, it is allowed to write a zeroed dword
on unerased flash.
Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
When using the settings subsystem, the data argument argument passed to
flash_stm32_write_range() might not be 8-bytes aligned, causing an
unaligned memory access fault.
Fix that the same way as it was done for the STM32L4 in commit
652efa530f.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit fixes dual bank flash handling on stm32g0 targets.
In contrast to other Series (G4, L5) the flash page size does not change
in single bank configuration (2KiB in both configurations).
nSWAP_BANK:
While the reference manual(RM) only documents:
"This bit selects the bank that is the subject of empty check upon boot"
as expected, this behaves similar to BFB2 on G4 and SWAP_BANK on L5.
It has been observed that this bit swaps the address mapping of bank1
and bank2, regardless of DUAL_BANK bit being set or not.
As documented in the RM the nSWAP_BANK bit is ignored when the BOOT_LOOK
bit is set. This applies to the empty check as well as the address
mapping.
On this Series FLASH_CR_BKER must be set in single-bank as well as
dual-bank configuration for erase operations on bank2 regardless of
the swap status.
On a G0B1RE (dev-id: 0x467) I could not observe a difference between
DUAL_BANK flash option bit set and not.
It this may be different on 256KiB Flash targets.
The HAL indicates that "FLASH_SALES_TYPE_0" only uses a single bank if
OB_DUAL_BANK_VALUE is not set, but as I don't know which SoC this is
and I can't test the behaviour and the driver does not take this into
account.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit makes no functional changes, it only refactors the
driver such that dual bank flash handling can be easily added.
Instead of using HAL macros directly in the code, new macros
with STM32G0 prefix are defined.
The erase_page function gets passed the offset instead of the page,
and the FLASH CR reg is written once with all erase parameters.
flash_stm32_wait_flash_idle is already called before each
write to CR, consequently it is also made sure CFGBSY flag
is not set.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit fixes sporadic kernel panics when writing big data chunks
to the flash. (data bus errors). Just like the stm32g4 does
but on instruction cache.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Remove soc/arm/st_stm32/stm32YY/flash_registers.h files.
Change register accesses in stm32 flash drivers to use FLASH_TypeDef
from modules/hal/stm32/stm32cube/stm32YYxx/soc/stm32xxxxxx.h.
Fixes#16235
Signed-off-by: Sarvesh Patkar <psarvesh314@gmail.com>
The build infrastructure should not be adding the drivers subdirectory
to the include path. Fix the legacy uses that depended on that
addition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add flash support for STM32G0X SoC series.
Signed-off-by: Philippe Retornaz <philippe@shapescale.com
Signed-off-by: Francois Ramu <francois.ramu@st.com>
move flash.h to drivers/flash.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
STM32F0 flash driver already uses FLASH_PAGE_SIZE from HAL
in flash layout part, so CONFIG_FLASH_PAGE_SIZE is redundant
and confusing.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
Add the STM32F0 Embedded Flash support in the flash_stm32 driver
interface.
The STM32F0 has a particularity or use the HSI as clock source
for the flash controller interface, so this clock must be
enabled directly in the case HSE or another clock is used by
the system clock.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
L4 parts have a constant page size, so just rely on the HAL defines
that provide it, along with a read to the register which contains this
SoC's total size.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
This is a prep work commit for adding flash page layout support.
The internal flash APIs for STM32 on L4 and F4 are a bit
inconsistent. Some routines take a pointer to the private data, others
don't. Those that do take it as a last argument instead of a
first. Additionally, some APIs are declared in flash_stm32.h that
aren't ever used by the family-specific files.
Clean this up by making everything take a struct device*, and marking
routines static in the common driver code when possible.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
L4 write access requires 64 bits alignment
while L4 read access does not require any alignment.
To support specific check according to read/write,erase
a parameter is added to stm32_valid_range.
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
L4 have 64 bits write access.
The cast to 64 bits data address in write_dword
requires 3 right shifts on i (byte index) else the
data taken are wrong for i different from 0
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
The STM32L4x SoCs embeds a slightly different embedded flash controller
from the STM32F4x SoCs.
This particular controller has the following properties :
- Up to 2 512KiB banks divided in 2KiB pages
- Flash can be accessed in any sizes
- Flash must be written in 64bit aligned 64bit double-words
The drivers/flash/flash_stm32f4x.c is refactored into a new common
drivers/flash/flash_stm32.c and drivers/flash/flash_stm32l4x.c is
created with the STM32L4x specific functions.
To ease the refactoring and keep common functions, the STM32L4x flash
headers are slightly modified to match the hardware reference naming
and solve compilation issues.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Francois Ramu
Andrew Sonzogni
Florian Vaussard
Cyril Fougeray
Aurelien Jarno
Gerard Marull-Paretas
Thomas Stranger
Tomasz Bursztyka
Kumar Gala
Sarvesh Patkar
Peter Bigot
Anas Nashif
Patrik Flykt
Ilya Tagunov
Neil Armstrong
Marti Bolivar
Michel Jaouen