Add STM32_FOO_ENABLED and STM32_FOO_FREQ to STM32 fixed clocks:
HSI, HSE, MSI(S), CSI, LSI, LSE..
Replace STM32_LSE_CLOCK by STM32_LSE_FREQ and when possible
replace by new STM32_LSE_ENABLED when making sense.
Fix STM32_PLL3_FOO_ENABLE to STM32_PLL3_FOO_ENABLED
Additionally, add STM32_PLL_FOO_ENABLED definitions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Recent changes in this function made the code now compatible
with the use of LL API to perform this configuration.
Use it to simplify the driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Voltage scaling computation should be done in multiple cases.
Add a function that takes into account all cases.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In case of MSIS selected as system clock source it is necessary
to set Voltage scaling (VOS) when freqency is greater than 24MHz
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
When MSI trimming values where set to 0,
and MSIS is used as system core clock and MSI > 4 MHz,
it causes uart to fail.
There is no need to set thoses trimming values.
So keep the default reset value. (keep ST Factory calibration)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Because on stm32u5 MSIS is the default clock after reset,
changing MSIS range means immediate frequency change.
Thus it is important to do it after flash latency change
in case of higher new frequency.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Refactors all of the clock control drivers to use a shared driver class
initialization priority configuration,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control
drivers separately from other devices. This is similar to other driver
classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
The even lower defaults for STM32 and Arm Beetle are preserved by
SoC-family level overrides.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
When existing stop mode 1&2, VCO is set to range 4
and should be set back to range 1 to allow full speed
operations.
Rather than setting VCO at startup, set it inside clock
setting procedure so that it could done
in clock reset procedure when existing stop modes.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This constraint on the AHB prescaler is removed.
The ahb-prescaler is allow from 1-512.
For stm32 common and stm32U5 devices.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Enable PWR clock unconditionally for L4, L5 and U5
like it is done on other stm32 series
Fixes#37781
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Add clock_control driver to stm32u5 support.
For this series, now deprecated STM32 clock Kconfig symbols
are not added.
Due to a divergence in MSI clock definition, PLL1 use
instead of PLL and lack of sufficient abstraction abstraction
for these a dedicated file has been added.
This should be reshuffled:
- once a better abstraction is provided by LL API for these
- when some stm32 clock control driver rework will be done
after complete removal of Kconfig STM32 clock symbols.
Tested in MSI, HSI, PLL based HSI and PLL based MSI.
Not tested on HSE due to lack of compatible hardware.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Erwan Gouriou
Nazar Kazakov
Alexandre Bourdiol
Maureen Helm
Francois Ramu