Make the LSE driving capability configurable for the STM32 series.
Fixes#44737.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
STM32H7 series offer alias addresses to access some registers that could
be accessed by the M4 core on dual core variants.
For instance RCC_AHB3ENR could be accessed at following offsets:
- 0x0D4: Accessible from both cores
- 0x134: Accessible from C1 (M7) core
- 0x194: Accessible from C2 (M4) core (if any)
For most single core H7 variants, the two first addresses were accessible,
but for some others (stm32h7ax/stm32h7bx), only the 'C1 accessible'
was available.
This fact used to be hidden by the use of LL API to access these registers,
providing the required abstraction (an mainly using the first alias
when possible to simplify implementation).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Set bus binding values using registers offset values.
As a consequence update driver to take this into account
in clock_on and clock_off functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of reading registers query the info on sysclock configuration
from existing configuration symbols.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rework clock start up functions in order to allow configuration
and enabling of individual clocks.
This way, each clock defined with a "okay" status will be enabled
even if not part of the sysclock clock tree.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add STM32_FOO_ENABLED and STM32_FOO_FREQ to STM32 fixed clocks:
HSI, HSE, MSI(S), CSI, LSI, LSE..
Replace STM32_LSE_CLOCK by STM32_LSE_FREQ and when possible
replace by new STM32_LSE_ENABLED when making sense.
Fix STM32_PLL3_FOO_ENABLE to STM32_PLL3_FOO_ENABLED
Additionally, add STM32_PLL_FOO_ENABLED definitions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
PLL3 setting should also be protected CFG_HW_RCC_SEMID.
Move semaphore unlock after we're done with PLL3.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32H7B3 supports max SYSCLK and AHB clock frequencies of 280 MHz,
and max APB frequency of 140 MHz
Signed-off-by: Tomislav Milkovic <tomislav.milkovic95@gmail.com>
STM32H7 has different power supply modes but now Zephyr supports just LDO
and direct SMPS. This commit introduses POWER_SUPPLY_CHOICE configuration
parameter and add support for missed power supply modes.
Signed-off-by: Gennady Kovalev <gik@bigur.com>
Fixes#40730.
Refactors all of the clock control drivers to use a shared driver class
initialization priority configuration,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control
drivers separately from other devices. This is similar to other driver
classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
The even lower defaults for STM32 and Arm Beetle are preserved by
SoC-family level overrides.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Update stm32h7 clock_control driver to make use of macros allowing
dts based configuration in coexistance with existing Kconfig method.
Note: Use of IS_ENABLED is removed as it generates warnings in
checkpatch. This checkpatch behavior needs to be reviewed but may
first require a little clean up of IS_ENABLED macro.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added support for STM32H753XX by adding CONFIG_SOC_STM32H753XX to list
of H7 SoC with maximum 480MHz SYSCLK.
Signed-off-by: Jeremy Wood <jeremy@bcdevices.com>
Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3
is used as a clock source by certain peripherals, e.g. LTDC.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Provide a utility function to compute PLL VCO input range so that it
can be re-used for other PLLs.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Line break on #error directive is confusing github and ending up
breaking syntax highligthing in github UI which makes me nervous
during review.
Convert error message to a one liner.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert clock_control drivers from:
DEVICE_AND_API_INIT -> DEVICE_DT_DEFINE
As part of this we also changed STM32_CLOCK_CONTROL_NAME to be based on
devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
VCO input frequency can be checked and set during compile time.
It unfortunately does not work for output frequency because macros in
HAL are defined together with uint32_t type.
This also fixes wrong check in case of HSI used as PLL source.
Signed-off-by: Jan Pohanka <xhpohanka@gmail.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add HSI divisor support for clock tree configuration.
Removed HSI calibration trimming to comply with
common STM32 implementation and use reset default
configuration instead.
Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
Adds preprocessor clock feasibility check to avoid setting
too high clocks to SYSCLK,AHB,APBx buses.
Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
matches with the desired clock configuration by
the M7 core.
Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
Fixed wrong usage of assertions.
Assertions should check that the value is in range and
not out of range.
Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
Fixes#27212 by setting the AHB/APBx dividers
prior to configuring the PLL as clock source.
Prevents going over the limits of APBx clocks when
choosing the PLL as system clock source for
high frequencies (close to 480MHz)
Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
Add HSE,HSI,CSI,PLL as system clock options.
Also add correct configuration of the PLL.
New sysclk options:
- HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y
- HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y
- CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y
Existing sysclk options:
- PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
PLL clock options:
- More PLL source clocks:
Existing:
1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
New:
2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y
- PLL vco input range is auto-calculated based on PLL DIVM1
-> Example for sysclock 96MHz generated with PLL from HSI
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h
instead to setup the correct latency.
Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
In case of dualcore, STM32H7, STM32W and STM32MP1,
protect concurrent register write access with HSEM.
Done for following drivers:
clock_control, counter, flash, gpio, interrupt_controller
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
On cortex M4, AHB clock is equal to SystemCoreClock
On Cortex M7, AHB clock is equal to SystemCoreClock/HPRE
By the way, D1CPRE is of no use when starting from SystemCoreColck.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Move PWR init code out of clock control driver and
put SMPS related function under SMPS condition as it
is not supported by all soc variants of the series.
Fixes#22363
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The build infrastructure should not be adding the drivers subdirectory
to the include path. Fix the legacy uses that depended on that
addition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The build infrastructure should not be adding the drivers subdirectory
to the include path. Fix the legacy uses that depended on that
addition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
STM32 clock control subsystem allows to configure a different
frequency value for core clock (SYSCLK) and AHB clock (HCLK).
Though, it is HCLK which is used to feed Cortex Systick timer
which is used in zephyr as reference system clock.
If HCLK frequency is configured to a different value from SYSCLK
frequency, whole system is exposed to desynchro between zephyr clock
subsytem and STM32 HW configuration.
To prevent this, and until zephyr clock subsystem is changed to be
aware of this potential configuration, enforce AHB prescaler value
to 1 (which is current default value in use for all STM32 based
boards).
On STM32H7, enforce D1CPRE which fills the same role as ABH precaler.
On STM32MP1, the equivalent setting is done on A7 core, so it is
not exposed to the same issue as long as SYS_CLOCK_HW_CYCLES_PER_SEC
is set with the 'mlhclk_ck' clock frequency value. Update
matching boards documentation.
Fixes#17188
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On STM32H7, in Dual core configuration, we restrict configuration
access to CM7 core. CM4 can access to API but not the init part of
the driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Provide basic clock control driver for STM32H7.
Bus clock activation is done through CM7 and CM4 common registers
so we don't have to care to the CPU Id before accessing.
Accesses are not protected for now. Only possible configuration
is system clock source set to HSE driven PLL.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Benedikt Schmidt
Erwan Gouriou
Nazar Kazakov
Tomislav Milkovic
Mikkel Jakobsen
Manojkumar Subramaniam
Gennady Kovalev
Maureen Helm
Oliver Yang
Gerard Marull-Paretas
Jeremy Wood
Gerard Marull-Paretas
Kumar Gala
Martin Jäger
Alexander Kozhinov
Jan Pohanka
Tomasz Bursztyka
Jeremy LOCHE
Alexandre Bourdiol
Peter Bigot