This commit fixes the incorrect code formatting used by target_riscv.cmake
by changing the 4-space indent to 2-space and removing the space between if
keyword and parenthesis.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The QingKe V2C has an integer multiplier but no divide. Add support
for the corresponding Zmmul extension and, as the extension was added
in GCC 13.0, add a test for the compiler version.
Signed-off-by: Michael Hope <michaelh@juju.nz>
On RISC-V, GCC and possibly other compilers include small globals in
special "small data" sections like .sbss and .sdata.
This allows accessing these globals using the global pointer register
and an offset, which is faster than ordinary relocations.
Currently, llext_load does not support multiple NOBIT sections.
Thus, llext's that use both .bss and .sbss sections cannot be relocated.
Also, the global pointer cannot be used in llext's, as it does not
change when calling into or returning from an llext, making the
optimization pointless for llext.
This commit disables the use of small data sections by adding the
appropriate compiler flag when compiling llext's.
In addition to solving the aforementioned issue, this fixes llext's
test_inspect on RISC-V.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The Zaamo and Zalrsc Extension (Version v1.0.0, 2024-04-25; Ratified) split
the standard A extension into two subextensions. As of date, the `_zaamo`
and `_zlrsc` extension specifications are accepted by the upstream
in-development GCC through the `march` argument. This means that those
subextensions are not yet supported by GCC shipped with Zephyr SDK.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit introduces architecture-specific ELF relocations for RISC-V,
in accordance with the RISC-V PSABI specification:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
Also, the necessary compiler configurations for compiling LLEXT
extensions on RISC-V are added, and the llext tests are executed on
RISC-V targets.
Calling llext extensions from user threads in RISC-V is still
unsupported as of this commit.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
This patch is doing several things:
- Core ISA and extension Kconfig symbols have now a formalized name
(CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*)
- a new Kconfig.isa file was introduced with the full set of extensions
currently supported by the v2.2 spec
- a new Kconfig.core file was introduced to host all the RISCV cores
(currently only E31)
- ISA and extensions settings are moved to SoC configuration files
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
New KConfig options for 'A' and 'M' RISC-V extensions have been
added. These are used to configure the '-march' string used by GCC
to produce a compatible binary for the requested RISC-V variant.
In order to maintain compatibility with all currently defined SoC,
default the options for HW mul / Atomics support to 'y', but allow
them to be overridden for any SoC which does not support these.
I tested this change locally via twister agaisnt a few RISC-V platforms
including some 32bit and 64bit. To verify the 4 possibilities of Atomics
& HW Mul: (No, No), (No, Yes), (Yes, No), (Yes, Yes -- current behavior),
I used an out-of-tree GCC (xPack RISC-V GCC) which has multilib support
for rv32i, rv32ia, rv32ima to test against our out-of-tree Intel Nios V/m
processor in HW. The Zephyr SDK RISCV GCC currently does not contain
multilib support for all variants exposed by these new KConfig options.
Signed-off-by: Nathan Krueger <nathan.krueger@intel.com>
We compile objects with -mcmodel=medany. Now also give -mcmodel=medany
to the GCC front-end when linking to pick up the corresponding
multilibs.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Fixes#28456
This commit extends `target_ld_options()` with a NO_SPLIT flag.
Specifying `NO_SPLIT` will ensure that all linker flags will be applied
together when testing the compiler and linker.
This allows a caller to ensure that flags are tested together.
This fixes the RISC-V case where the flags `-mabi` and `-march` were
omitted because they were tested individually.
Note, the update of `target_ld_options()` will allow the same flag on
`zephyr_ld_options()`
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit renames the Kconfig `FLOAT` symbol to `FPU`, since this
symbol only indicates that the hardware Floating Point Unit (FPU) is
used and does not imply and/or indicate the general availability of
toolchain-level floating point support (i.e. this symbol is not
selected when building for an FPU-less platform that supports floating
point operations through the toolchain-provided software floating point
library).
Moreover, given that the symbol that indicates the availability of FPU
is named `CPU_HAS_FPU`, it only makes sense to use "FPU" in the name of
the symbol that enables the FPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Adds handling of the FLOAT_64BIT option when determining the ISA
flags as well as introduces a new Kconfig option to enable/disable
the hard-float calling convention.
Signed-off-by: Corey Wharton <coreyw7@fb.com>
The mabi and march options of the compiler and linker commands
were previously hardcoded and depended only on the 64BIT config
option. This update allows these flags to be set by the config
options currently available, plus an additional option to
specify the compressed ISA.
Signed-off-by: Jaron Kelleher <jkelleher@fb.com>
Stephanos Ioannidis
Marcin Szymczyk
Michael Hope
Eric Ackermann
Filip Kokosinski
Carlo Caione
Nathan Krueger
Martin Åberg
Torsten Rasmussen
Corey Wharton
Jaron Kelleher