soc: fvp_aemv8r_aarch32: Port to HWMv2

Ports the fvp_aemv8r_aarch32 SoC configuration to hardware model
version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

soc/arm/fvp_aemv8r/CMakeLists.txt

@@ -1,11 +1,14 @@
 # Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
-zephyr_library_sources(
+if(CONFIG_SOC_FVP_AEMV8R_AARCH64)
-  soc.c
+  zephyr_library_sources(aarch64/soc.c)
-)
+  zephyr_library_sources_ifdef(CONFIG_ARM_MPU aarch64/arm_mpu_regions.c)
 
-zephyr_library_sources_ifdef(CONFIG_ARM_MPU arm_mpu_regions.c)
+  set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")
+elseif(CONFIG_SOC_FVP_AEMV8R_AARCH32)
+  zephyr_library_sources_ifdef(CONFIG_ARM_MPU aarch32/arm_mpu_regions.c)
+  zephyr_library_sources(aarch32/soc.c)
+  zephyr_include_directories(aarch32)
 
-zephyr_include_directories(.)
+  set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
-
+endif()
-set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")

soc/arm/fvp_aemv8r/Kconfig

@@ -1,13 +1,18 @@
 # Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_FVP_AEMV8R
-	select ARM64
-	help
-	  Enable support for ARM FVP AEMv8R AArch64 Series
-
 config SOC_FVP_AEMV8R_AARCH64
-	select SOC_SERIES_FVP_AEMV8R
 	select CPU_CORTEX_R82
 	select CPU_HAS_MPU
 	select GIC_SINGLE_SECURITY_STATE
+	select ARM64
+
+config SOC_FVP_AEMV8R_AARCH32
+	select CPU_CORTEX_R52
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_MPU
+	select VFP_DP_D32_FP16_FMAC if !USE_SWITCH
+	select GIC_V3
+	select GIC_SINGLE_SECURITY_STATE
+	select PLATFORM_SPECIFIC_INIT
+	select ARM

soc/arm/fvp_aemv8r/Kconfig.defconfig

@@ -9,8 +9,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config NUM_IRQS
 	default 128
 
-if SOC_FVP_AEMV8R_AARCH64
-
 # Workaround for not being able to have commas in macro arguments
 DT_CHOSEN_Z_FLASH := zephyr,flash
 
@@ -21,8 +19,7 @@ config FLASH_BASE_ADDRESS
 	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
 
 config MAX_DOMAIN_PARTITIONS
-	default 8
+	default 8 if SOC_FVP_AEMV8R_AARCH64
-
+	default 24 if USERSPACE && SOC_FVP_AEMV8R_AARCH32
-endif # SOC_FVP_AEMV8R_AARCH64
 
 endif # SOC_SERIES_FVP_AEMV8R

soc/arm/fvp_aemv8r/Kconfig.soc

@@ -3,14 +3,22 @@
 
 config SOC_SERIES_FVP_AEMV8R
 	bool
-	select SOC_FAMILY_ARM64
+	help
+	  Enable support for ARM FVP AEMv8R AArch64 Series
 
 config SOC_FVP_AEMV8R_AARCH64
 	bool
+	select SOC_SERIES_FVP_AEMV8R
+	select SOC_FAMILY_ARM64
+
+config SOC_FVP_AEMV8R_AARCH32
+	bool
+	select SOC_SERIES_FVP_AEMV8R
+	select SOC_FAMILY_ARM
 
 config SOC_FVP_AEMV8R_SIMULATE_CPU_PM
 	bool "Simulate CPU Power Management for FVP_BaseR_AEMv8R"
-	default n
+	depends on SOC_FVP_AEMV8R_AARCH64
 	help
 	  It simulates the cpu power management function for
 	  FVP_BaseR_AEMv8R. When zephyr kernel try to bring up secondary
@@ -22,3 +30,4 @@ config SOC_SERIES
 
 config SOC
 	default "fvp_aemv8r_aarch64" if SOC_FVP_AEMV8R_AARCH64
+	default "fvp_aemv8r_aarch32" if SOC_FVP_AEMV8R_AARCH32

soc/arm/soc.yml

@@ -23,6 +23,7 @@ family:
   - name: fvp_aemv8r
     socs:
     - name: fvp_aemv8r_aarch64
+    - name: fvp_aemv8r_aarch32
   socs:
   - name: qemu_cortex_a53
   - name: qemu_virt_arm64

soc/soc_legacy/arm/arm/fvp_aemv8r_aarch32/CMakeLists.txt

@@ -1,7 +0,0 @@
-# Copyright (c) 2022 IoT.bzh
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library_sources_ifdef(CONFIG_ARM_MPU arm_mpu_regions.c)
-zephyr_library_sources(soc.c)
-
-set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")

soc/soc_legacy/arm/arm/fvp_aemv8r_aarch32/Kconfig.defconfig.series

@@ -1,34 +0,0 @@
-# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_FVP_AEMV8R_AARCH32
-
-config SOC_SERIES
-	default "fvp_aemv8r_aarch32"
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 100000000
-
-config NUM_IRQS
-	default 128
-
-if SOC_FVP_AEMV8R_AARCH32
-
-config SOC
-	default "fvp_aemv8r_aarch32"
-
-# Workaround for not being able to have commas in macro arguments
-DT_CHOSEN_Z_FLASH := zephyr,flash
-
-config FLASH_SIZE
-	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
-
-config FLASH_BASE_ADDRESS
-	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
-
-config MAX_DOMAIN_PARTITIONS
-	default 24 if USERSPACE
-
-endif # SOC_FVP_AEMV8R_AARCH32
-
-endif # SOC_SERIES_FVP_AEMV8R_AARCH32

soc/soc_legacy/arm/arm/fvp_aemv8r_aarch32/Kconfig.series

@@ -1,9 +0,0 @@
-# Copyright (c) 2022 IoT.bzh
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_FVP_AEMV8R_AARCH32
-	bool "ARM FVP AEMv8R AArch32 Series"
-	select ARM
-	select SOC_FAMILY_ARM
-	help
-	  Enable support for ARM FVP AEMv8R AArch32 Series

soc/soc_legacy/arm/arm/fvp_aemv8r_aarch32/Kconfig.soc

@@ -1,18 +0,0 @@
-# Copyright (c) 2022 IoT.bzh
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "ARM FVP AEMv8R AArch32 SoCs"
-	depends on SOC_SERIES_FVP_AEMV8R_AARCH32
-
-config SOC_FVP_AEMV8R_AARCH32
-	bool "ARM FVP AEMv8R aarch32 simulation"
-	select CPU_CORTEX_R52
-	select CPU_HAS_ARM_MPU
-	select CPU_HAS_MPU
-	select VFP_DP_D32_FP16_FMAC if !USE_SWITCH
-	select GIC_V3
-	select GIC_SINGLE_SECURITY_STATE
-	select PLATFORM_SPECIFIC_INIT
-
-endchoice