diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 60e1741f2b7..6e0747667a8 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -52,5 +52,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_AFIO pinctrl_wch_afio.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SY1XX pinctrl_sy1xx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_REALTEK_RTS5912 pinctrl_realtek_rts5912.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_20X_30X_AFIO pinctrl_wch_20x_30x_afio.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_00X_AFIO pinctrl_wch_00x_afio.c) add_subdirectory(renesas) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 9cdbfd42444..df6ab582e0e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -79,6 +79,7 @@ source "drivers/pinctrl/Kconfig.wch_afio" source "drivers/pinctrl/Kconfig.sy1xx" source "drivers/pinctrl/Kconfig.realtek_rts5912" source "drivers/pinctrl/Kconfig.wch_20x_30x_afio" +source "drivers/pinctrl/Kconfig.wch_00x_afio" rsource "renesas/Kconfig" diff --git a/drivers/pinctrl/Kconfig.wch_00x_afio b/drivers/pinctrl/Kconfig.wch_00x_afio new file mode 100644 index 00000000000..c581abc7dcd --- /dev/null +++ b/drivers/pinctrl/Kconfig.wch_00x_afio @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_WCH_00X_AFIO + bool "WCH AFIO pin controller driver for CH32V00x" + default y + depends on DT_HAS_WCH_00X_AFIO_ENABLED + help + WCH CH32V00x AFIO pin controller driver, excluding the CH32V003. diff --git a/drivers/pinctrl/pinctrl_wch_00x_afio.c b/drivers/pinctrl/pinctrl_wch_00x_afio.c new file mode 100644 index 00000000000..76fb682e4ca --- /dev/null +++ b/drivers/pinctrl/pinctrl_wch_00x_afio.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2025 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT wch_00x_afio + +#include +#include +#include + +#include + +static GPIO_TypeDef *const wch_afio_pinctrl_regs[] = { + (GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpioa)), + (GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpiob)), + (GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpioc)), + (GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpiod)), +}; + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + int i; + + for (i = 0; i < pin_cnt; i++, pins++) { + uint8_t port = FIELD_GET(CH32V00X_PINCTRL_PORT_MASK, pins->config); + uint8_t pin = FIELD_GET(CH32V00X_PINCTRL_PIN_MASK, pins->config); + uint8_t bit0 = FIELD_GET(CH32V00X_PINCTRL_BASE_MASK, pins->config); + uint8_t remap = FIELD_GET(CH32V00X_PINCTRL_RM_MASK, pins->config); + GPIO_TypeDef *regs = wch_afio_pinctrl_regs[port]; + uint8_t cfg = 0; + + if (pins->output_high || pins->output_low) { + cfg |= BIT(0); + if (pins->drive_open_drain) { + cfg |= BIT(2); + } + /* Select the alternate function */ + cfg |= BIT(3); + } else { + if (pins->bias_pull_up || pins->bias_pull_down) { + cfg |= BIT(3); + } + } + regs->CFGLR = (regs->CFGLR & ~(0x0F << (pin * 4))) | (cfg << (pin * 4)); + + if (pins->output_high) { + regs->OUTDR |= BIT(pin); + regs->BSHR |= BIT(pin); + } else if (pins->output_low) { + regs->OUTDR |= BIT(pin); + /* Reset the pin. */ + regs->BSHR |= BIT(pin + 16); + } else { + regs->OUTDR &= ~(1 << pin); + if (pins->bias_pull_up) { + regs->BSHR = BIT(pin); + } + if (pins->bias_pull_down) { + regs->BCR = BIT(pin); + } + } + + AFIO->PCFR1 |= remap << bit0; + } + + return 0; +} + +static int pinctrl_clock_init(void) +{ + const struct device *clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)); + uint8_t clock_id = DT_INST_CLOCKS_CELL(0, id); + + return clock_control_on(clock_dev, (clock_control_subsys_t *)(uintptr_t)clock_id); +} + +SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0); diff --git a/dts/bindings/pinctrl/wch,00x-afio.yaml b/dts/bindings/pinctrl/wch,00x-afio.yaml new file mode 100644 index 00000000000..a3a801e0527 --- /dev/null +++ b/dts/bindings/pinctrl/wch,00x-afio.yaml @@ -0,0 +1,50 @@ +# Copyright (c) 2025 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +description: WCH CH32V00x Alternate Function (AFIO) + +compatible: "wch,00x-afio" + +include: base.yaml + +properties: + reg: + required: true + "#address-cells": + required: true + const: 1 + "#size-cells": + required: true + const: 1 + +child-binding: + description: | + Each child node defines the configuration for a particular state. + child-binding: + description: | + The grandchild nodes group pins that share the same pin configuration. + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-high-impedance + - bias-pull-up + - bias-pull-down + - drive-open-drain + - drive-push-pull + - output-high + - output-low + + properties: + slew-rate: + type: string + default: "max-speed-30mhz" + enum: + - "max-speed-30mhz" + + pinmux: + required: true + type: array + description: | + An array of pins sharing the same group properties. The pins should + be defined using pre-defined macros. diff --git a/include/zephyr/dt-bindings/pinctrl/ch32v00x-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ch32v00x-pinctrl.h new file mode 100644 index 00000000000..f229efa9f94 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/ch32v00x-pinctrl.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2025 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __CH32V00X_PINCTRL_H__ +#define __CH32V00X_PINCTRL_H__ + +#define CH32V00X_PINMUX_PORT_PA 0 +#define CH32V00X_PINMUX_PORT_PB 1 +#define CH32V00X_PINMUX_PORT_PC 2 +#define CH32V00X_PINMUX_PORT_PD 3 + +/* Starting bit for the remap field in PCFR1 */ +#define CH32V00X_PINMUX_SPI1_RM 0 +#define CH32V00X_PINMUX_I2C1_RM 3 +#define CH32V00X_PINMUX_USART1_RM 6 +#define CH32V00X_PINMUX_TIM1_RM 10 +#define CH32V00X_PINMUX_TIM2_RM 14 +#define CH32V00X_PINMUX_PA1PA2_RM 17 +#define CH32V00X_PINMUX_ADC_DTR_GINJ_RM 18 +#define CH32V00X_PINMUX_ADC_DTR_GREG_RM 19 +#define CH32V00X_PINMUX_USART2_RM 20 + +/* Port number with 0-3 */ +#define CH32V00X_PINCTRL_PORT_SHIFT 0 +#define CH32V00X_PINCTRL_PORT_MASK GENMASK(1, 0) +/* Pin number 0-7 */ +#define CH32V00X_PINCTRL_PIN_SHIFT 2 +#define CH32V00X_PINCTRL_PIN_MASK GENMASK(4, 2) +/* Base remap bit 0-31 */ +#define CH32V00X_PINCTRL_BASE_SHIFT 5 +#define CH32V00X_PINCTRL_BASE_MASK GENMASK(9, 5) +/* Function remapping ID 0-7 */ +#define CH32V00X_PINCTRL_RM_SHIFT 10 +#define CH32V00X_PINCTRL_RM_MASK GENMASK(12, 10) + +#define CH32V00X_PINMUX_DEFINE(port, pin, rm, remapping) \ + ((CH32V00X_PINMUX_PORT_##port << CH32V00X_PINCTRL_PORT_SHIFT) | \ + (pin << CH32V00X_PINCTRL_PIN_SHIFT) | \ + (CH32V00X_PINMUX_##rm##_RM << CH32V00X_PINCTRL_BASE_SHIFT) | \ + (remapping << CH32V00X_PINCTRL_RM_SHIFT)) + +#define TIM1_ETR_PC5_0 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 0) +#define TIM1_ETR_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 1) +#define TIM1_ETR_PD4_2 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 2) +#define TIM1_ETR_PC2_3 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 3) +#define TIM1_CH1_PD2_0 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 0) +#define TIM1_CH1_PC6_1 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 1) +#define TIM1_CH1_PD2_2 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 2) +#define TIM1_CH1_PC4_3 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 3) +#define TIM1_CH2_PA1_0 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 0) +#define TIM1_CH2_PC7_1 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 1) +#define TIM1_CH2_PA1_2 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 2) +#define TIM1_CH2_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 3) +#define TIM1_CH3_PC3_0 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 0) +#define TIM1_CH3_PC0_1 CH32V00X_PINMUX_DEFINE(PC, 0, TIM1, 1) +#define TIM1_CH3_PC3_2 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 2) +#define TIM1_CH3_PC5_3 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 3) +#define TIM1_CH4_PC4_0 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 0) +#define TIM1_CH4_PD3_1 CH32V00X_PINMUX_DEFINE(PD, 3, TIM1, 1) +#define TIM1_CH4_PC4_2 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 2) +#define TIM1_CH4_PD4_3 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 3) +#define TIM1_BKIN_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 0) +#define TIM1_BKIN_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 1) +#define TIM1_BKIN_PC2_2 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 2) +#define TIM1_BKIN_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 3) +#define TIM1_CH1N_PD0_0 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 0) +#define TIM1_CH1N_PC3_1 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 1) +#define TIM1_CH1N_PD0_2 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 2) +#define TIM1_CH1N_PC3_3 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 3) +#define TIM1_CH2N_PA2_0 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 0) +#define TIM1_CH2N_PC4_1 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 1) +#define TIM1_CH2N_PA2_2 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 2) +#define TIM1_CH2N_PD2_3 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 3) +#define TIM1_CH3N_PD1_0 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 0) +#define TIM1_CH3N_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 1) +#define TIM1_CH3N_PD1_2 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 2) +#define TIM1_CH3N_PC6_3 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 3) + +#define TIM2_ETR_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 0) +#define TIM2_ETR_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 1) +#define TIM2_ETR_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 2) +#define TIM2_ETR_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 3) +#define TIM2_CH1_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 0) +#define TIM2_CH1_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 1) +#define TIM2_CH1_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 2) +#define TIM2_CH1_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 3) +#define TIM2_CH2_PD3_0 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 0) +#define TIM2_CH2_PC2_1 CH32V00X_PINMUX_DEFINE(PC, 2, TIM2, 1) +#define TIM2_CH2_PD3_2 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 2) +#define TIM2_CH2_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, TIM2, 3) +#define TIM2_CH3_PC0_0 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 0) +#define TIM2_CH3_PD2_1 CH32V00X_PINMUX_DEFINE(PD, 2, TIM2, 1) +#define TIM2_CH3_PC0_2 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 2) +#define TIM2_CH3_PD6_3 CH32V00X_PINMUX_DEFINE(PD, 6, TIM2, 3) +#define TIM2_CH4_PD7_0 CH32V00X_PINMUX_DEFINE(PD, 7, TIM2, 0) +#define TIM2_CH4_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 1) +#define TIM2_CH4_PD7_2 CH32V00X_PINMUX_DEFINE(PD, 7, TIM2, 2) +#define TIM2_CH4_PD5_3 CH32V00X_PINMUX_DEFINE(PD, 5, TIM2, 3) + +#define USART1_CK_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, USART1, 0) +#define USART1_CK_PD7_1 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 1) +#define USART1_CK_PD7_2 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 2) +#define USART1_CK_PC5_3 CH32V00X_PINMUX_DEFINE(PC, 5, USART1, 3) +#define USART1_TX_PD5_0 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 0) +#define USART1_TX_PD0_1 CH32V00X_PINMUX_DEFINE(PD, 0, USART1, 1) +#define USART1_TX_PD6_2 CH32V00X_PINMUX_DEFINE(PD, 6, USART1, 2) +#define USART1_TX_PC0_3 CH32V00X_PINMUX_DEFINE(PC, 0, USART1, 3) +#define USART1_RX_PD6_0 CH32V00X_PINMUX_DEFINE(PD, 6, USART1, 0) +#define USART1_RX_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, USART1, 1) +#define USART1_RX_PD5_2 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 2) +#define USART1_RX_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, USART1, 3) +#define USART1_CTS_PD3_0 CH32V00X_PINMUX_DEFINE(PD, 3, USART1, 0) +#define USART1_CTS_PC3_1 CH32V00X_PINMUX_DEFINE(PC, 3, USART1, 1) +#define USART1_CTS_PC6_2 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 2) +#define USART1_CTS_PC6_3 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 3) +#define USART1_RTS_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, USART1, 0) +#define USART1_RTS_PC2_1 CH32V00X_PINMUX_DEFINE(PC, 2, USART1, 1) +#define USART1_RTS_PC7_2 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 2) +#define USART1_RTS_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 3) + +#define USART2_TX_PA7_0 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 0) +#define USART2_TX_PA4_1 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 1) +#define USART2_TX_PA2_2 CH32V00X_PINMUX_DEFINE(PA, 2, USART2, 2) +#define USART2_TX_PD2_3 CH32V00X_PINMUX_DEFINE(PD, 2, USART2, 3) +#define USART2_TX_PB0_4 CH32V00X_PINMUX_DEFINE(PB, 0, USART2, 4) +#define USART2_TX_PC4_5 CH32V00X_PINMUX_DEFINE(PC, 4, USART2, 5) +#define USART2_TX_PA6_6 CH32V00X_PINMUX_DEFINE(PA, 6, USART2, 6) +#define USART2_RX_PB3_0 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 0) +#define USART2_RX_PA5_1 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 1) +#define USART2_RX_PA3_2 CH32V00X_PINMUX_DEFINE(PA, 3, USART2, 2) +#define USART2_RX_PD3_3 CH32V00X_PINMUX_DEFINE(PD, 3, USART2, 3) +#define USART2_RX_PB1_4 CH32V00X_PINMUX_DEFINE(PB, 1, USART2, 4) +#define USART2_RX_PD1_5 CH32V00X_PINMUX_DEFINE(PD, 1, USART2, 5) +#define USART2_RX_PA5_6 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 6) +#define USART2_CTS_PA4_0 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 0) +#define USART2_CTS_PA7_1 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 1) +#define USART2_CTS_PA0_2 CH32V00X_PINMUX_DEFINE(PA, 0, USART2, 2) +#define USART2_CTS_PA0_3 CH32V00X_PINMUX_DEFINE(PA, 0, USART2, 3) +#define USART2_CTS_PB6_4 CH32V00X_PINMUX_DEFINE(PB, 6, USART2, 4) +#define USART2_CTS_PA4_5 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 5) +#define USART2_CTS_PA7_6 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 6) +#define USART2_RTS_PA5_0 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 0) +#define USART2_RTS_PB3_1 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 1) +#define USART2_RTS_PA1_2 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 2) +#define USART2_RTS_PA1_3 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 3) +#define USART2_RTS_PA1_4 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 4) +#define USART2_RTS_PA1_5 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 5) +#define USART2_RTS_PB3_6 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 6) + +#define SPI1_NSS_PC1_0 CH32V00X_PINMUX_DEFINE(PC, 1, SPI1, 0) +#define SPI1_NSS_PC0_1 CH32V00X_PINMUX_DEFINE(PC, 0, SPI1, 1) +#define SPI1_SCK_PC5_0 CH32V00X_PINMUX_DEFINE(PC, 5, SPI1, 0) +#define SPI1_SCK_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, SPI1, 1) +#define SPI1_MISO_PC7_0 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 0) +#define SPI1_MISO_PC7_1 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 1) +#define SPI1_MOSI_PC6_0 CH32V00X_PINMUX_DEFINE(PC, 6, SPI1, 0) +#define SPI1_MOSI_PC6_1 CH32V00X_PINMUX_DEFINE(PC, 6, SPI1, 1) + +#define I2C1_SCL_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, I2C1, 0) +#define I2C1_SCL_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, I2C1, 1) +#define I2C1_SCL_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, I2C1, 2) +#define I2C1_SDA_PC1_0 CH32V00X_PINMUX_DEFINE(PC, 1, I2C1, 0) +#define I2C1_SDA_PD0_1 CH32V00X_PINMUX_DEFINE(PD, 0, I2C1, 1) +#define I2C1_SDA_PC6_2 CH32V00X_PINMUX_DEFINE(PC, 6, I2C1, 2) + +#endif /* __CH32V00X_PINCTRL_H__ */