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Add adc driver for Realtek rts5912. Signed-off-by: Dylan Hsieh <dylan.hsieh@realtek.com>pull/88182/merge
Dylan Hsieh
4 months ago
committed by
Benjamin Cabé
12 changed files with 465 additions and 0 deletions
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# Copyright (c) 2025, Realtek, SIBG-SD7 |
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# SPDX-License-Identifier: Apache-2.0 |
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config ADC_REALTEK_RTS5912 |
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bool "Realtek RTS5912 ADC drivers" |
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default y |
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depends on DT_HAS_REALTEK_RTS5912_ADC_ENABLED |
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select PINCTRL |
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help |
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This option enables the ADC driver for Realtek RTS5912 of processors. |
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/*
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* Copyright (c) 2025 Realtek, SIBG-SD7 |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT realtek_rts5912_adc |
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#include <zephyr/drivers/adc.h> |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/drivers/clock_control/clock_control_rts5912.h> |
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#include <zephyr/drivers/pinctrl.h> |
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#include "reg/reg_adc.h" |
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#define ADC_CONTEXT_USES_KERNEL_TIMER |
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#include "adc_context.h" |
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#include <zephyr/logging/log.h> |
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LOG_MODULE_REGISTER(adc_rts5912, CONFIG_ADC_LOG_LEVEL); |
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#define RTS5912_ADC_MAX_CHAN 12 |
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#define RTS5912_ADC_POLLING_TIME_MS 1 |
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#define RTS5912_ADC_ENABLE_TIMEOUT 100 |
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struct adc_rts5912_config { |
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volatile struct adc_regs *regs; |
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const struct pinctrl_dev_config *pcfg; |
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#ifdef CONFIG_CLOCK_CONTROL |
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const struct device *clk_dev; |
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struct rts5912_sccon_subsys sccon_cfg; |
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#endif |
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}; |
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struct adc_rts5912_data { |
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struct adc_context ctx; |
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const struct device *adc_dev; |
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volatile uint16_t *buffer; |
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volatile uint16_t *repeat_buffer; |
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uint32_t channels; |
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}; |
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static void adc_context_start_sampling(struct adc_context *ctx) |
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{ |
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struct adc_rts5912_data *data = CONTAINER_OF(ctx, struct adc_rts5912_data, ctx); |
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const struct device *adc_dev = data->adc_dev; |
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const struct adc_rts5912_config *const cfg = adc_dev->config; |
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volatile struct adc_regs *regs = cfg->regs; |
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data->repeat_buffer = data->buffer; |
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regs->ctrl |= ADC_CTRL_SGLDNINTEN; |
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regs->ctrl |= ADC_CTRL_START; |
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} |
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static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling) |
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{ |
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struct adc_rts5912_data *data = CONTAINER_OF(ctx, struct adc_rts5912_data, ctx); |
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if (repeat_sampling) { |
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data->buffer = data->repeat_buffer; |
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} |
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} |
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static int adc_rts5912_channel_setup(const struct device *dev, |
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const struct adc_channel_cfg *channel_cfg) |
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{ |
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const struct adc_rts5912_config *const cfg = dev->config; |
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volatile struct adc_regs *regs = cfg->regs; |
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) { |
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LOG_ERR("Conversion time not supported!"); |
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return -EINVAL; |
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} |
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if (channel_cfg->channel_id >= RTS5912_ADC_MAX_CHAN) { |
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LOG_ERR("Channel %d not supported!", channel_cfg->channel_id); |
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return -EINVAL; |
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} |
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if (channel_cfg->gain != ADC_GAIN_1) { |
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LOG_ERR("ADC gain not supported!"); |
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return -EINVAL; |
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} |
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uint8_t channel_id = channel_cfg->channel_id; |
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regs->chctrl |= ((0x01ul << channel_id) | (ADC_CHCTRL_LPFBP << channel_id)); |
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LOG_DBG("CHCTRL = 0x%08x", regs->chctrl); |
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return 0; |
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} |
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static bool adc_rts5912_validate_buffer_size(const struct adc_sequence *sequence) |
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{ |
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int chan_count = 0; |
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size_t buff_need; |
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uint32_t chan_mask; |
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for (chan_mask = 0x80; chan_mask != 0; chan_mask >>= 1) { |
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if (chan_mask & sequence->channels) { |
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chan_count++; |
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} |
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} |
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buff_need = chan_count * sizeof(uint16_t); |
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if (sequence->options) { |
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buff_need *= 1 + sequence->options->extra_samplings; |
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} |
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if (buff_need > sequence->buffer_size) { |
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return false; |
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} |
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return true; |
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} |
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static int adc_rts5912_enable(const struct device *dev) |
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{ |
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const struct adc_rts5912_config *const cfg = dev->config; |
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volatile struct adc_regs *regs = cfg->regs; |
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int64_t st = k_uptime_get(); |
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regs->ctrl |= ADC_CTRL_EN; |
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while ((k_uptime_get() - st) < RTS5912_ADC_ENABLE_TIMEOUT) { |
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if (regs->sts & ADC_STS_RDY) { |
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return 0; |
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} |
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k_msleep(RTS5912_ADC_POLLING_TIME_MS); |
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} |
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LOG_ERR("ADC enable timeout"); |
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regs->ctrl &= ~ADC_CTRL_EN; |
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return -EIO; |
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} |
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static int adc_rts5912_start_read(const struct device *dev, const struct adc_sequence *sequence) |
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{ |
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struct adc_rts5912_data *const data = dev->data; |
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if (sequence->channels & ~BIT_MASK(RTS5912_ADC_MAX_CHAN)) { |
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LOG_ERR("Incorrect channels, bitmask 0x%x", sequence->channels); |
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return -EINVAL; |
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} |
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if (sequence->channels == 0UL) { |
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LOG_ERR("No channel selected"); |
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return -EINVAL; |
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} |
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if (!adc_rts5912_validate_buffer_size(sequence)) { |
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LOG_ERR("Incorrect buffer size"); |
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return -ENOMEM; |
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} |
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data->channels = sequence->channels; |
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data->buffer = sequence->buffer; |
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if (adc_rts5912_enable(dev) < 0) { |
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return -EIO; |
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} |
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adc_context_start_read(&data->ctx, sequence); |
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return adc_context_wait_for_completion(&data->ctx); |
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} |
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static int adc_rts5912_read(const struct device *dev, const struct adc_sequence *sequence) |
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{ |
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struct adc_rts5912_data *const data = dev->data; |
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int error; |
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adc_context_lock(&data->ctx, false, NULL); |
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error = adc_rts5912_start_read(dev, sequence); |
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adc_context_release(&data->ctx, error); |
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return error; |
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} |
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static void rts5912_adc_get_sample(const struct device *dev) |
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{ |
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const struct adc_rts5912_config *const cfg = dev->config; |
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volatile struct adc_regs *regs = cfg->regs; |
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struct adc_rts5912_data *const data = dev->data; |
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uint32_t idx; |
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uint32_t channels = data->channels; |
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uint32_t bit; |
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/*
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* Using the enabled channel bit set, from |
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* lowest channel number to highest, find out |
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* which channel is enabled and copy the ADC |
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* values from hardware registers to the data |
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* buffer. |
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*/ |
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bit = find_lsb_set(channels); |
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while (bit != 0) { |
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idx = bit - 1; |
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*data->buffer = ((uint16_t)regs->chdata[idx] & ADC_CHDATA_RESULT_Msk); |
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data->buffer++; |
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LOG_DBG("idx=%d, data=%x", idx, regs->chdata[idx]); |
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channels &= ~BIT(idx); |
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bit = find_lsb_set(channels); |
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} |
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} |
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static void adc_rts5912_single_isr(const struct device *dev) |
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{ |
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const struct adc_rts5912_config *const cfg = dev->config; |
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volatile struct adc_regs *regs = cfg->regs; |
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struct adc_rts5912_data *const data = dev->data; |
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if (regs->sts & ADC_STS_SGLDN) { |
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LOG_DBG("single done interrupt triggered."); |
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regs->ctrl &= ~(ADC_CTRL_SGLDNINTEN); |
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regs->sts &= regs->sts; |
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rts5912_adc_get_sample(dev); |
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regs->ctrl &= ~ADC_CTRL_EN; |
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adc_context_on_sampling_done(&data->ctx, dev); |
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} |
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} |
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static int adc_rts5912_init(const struct device *dev) |
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{ |
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const struct adc_rts5912_config *const cfg = dev->config; |
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struct adc_rts5912_data *const data = dev->data; |
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volatile struct adc_regs *regs = cfg->regs; |
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int ret; |
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data->adc_dev = dev; |
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); |
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if (ret != 0) { |
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LOG_ERR("rts5912 ADC pinctrl setup failed (%d)", ret); |
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return ret; |
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} |
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#ifdef CONFIG_CLOCK_CONTROL |
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if (!device_is_ready(cfg->clk_dev)) { |
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LOG_ERR("clock \"%s\" device not ready", cfg->clk_dev->name); |
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return -ENODEV; |
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} |
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ret = clock_control_on(cfg->clk_dev, (clock_control_subsys_t)&cfg->sccon_cfg); |
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if (ret != 0) { |
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LOG_ERR("clock power on fail"); |
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return ret; |
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} |
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#endif |
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regs->ctrl = ADC_CTRL_RST; |
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IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), adc_rts5912_single_isr, |
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DEVICE_DT_INST_GET(0), 0); |
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irq_enable(DT_INST_IRQN(0)); |
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adc_context_unlock_unconditionally(&data->ctx); |
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return 0; |
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} |
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#define DEV_CONFIG_CLK_DEV_INIT(n) \ |
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.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ |
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.sccon_cfg = { \ |
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.clk_grp = DT_INST_CLOCKS_CELL(n, clk_grp), \ |
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.clk_idx = DT_INST_CLOCKS_CELL(n, clk_idx), \ |
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} |
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#define ADC_RTS5912_INIT(n) \ |
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PINCTRL_DT_INST_DEFINE(n); \ |
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\ |
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static DEVICE_API(adc, adc_rts5912_api_##n) = { \ |
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.channel_setup = adc_rts5912_channel_setup, \ |
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.read = adc_rts5912_read, \ |
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.ref_internal = DT_INST_PROP(n, vref_mv), \ |
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}; \ |
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\ |
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static struct adc_rts5912_config adc_rts5912_dev_cfg_##n = { \ |
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.regs = (struct adc_regs *)(DT_INST_REG_ADDR(n)), \ |
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ |
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DEV_CONFIG_CLK_DEV_INIT(n)}; \ |
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\ |
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static struct adc_rts5912_data adc_rts5912_dev_data_##n = { \ |
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ADC_CONTEXT_INIT_TIMER(adc_rts5912_dev_data_##n, ctx), \ |
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ADC_CONTEXT_INIT_LOCK(adc_rts5912_dev_data_##n, ctx), \ |
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ADC_CONTEXT_INIT_SYNC(adc_rts5912_dev_data_##n, ctx), \ |
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}; \ |
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\ |
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DEVICE_DT_INST_DEFINE(n, adc_rts5912_init, NULL, &adc_rts5912_dev_data_##n, \ |
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&adc_rts5912_dev_cfg_##n, PRE_KERNEL_1, CONFIG_ADC_INIT_PRIORITY, \ |
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&adc_rts5912_api_##n); |
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DT_INST_FOREACH_STATUS_OKAY(ADC_RTS5912_INIT) |
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description: Realtek rts5912 ADC |
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compatible: "realtek,rts5912-adc" |
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include: [adc-controller.yaml, pinctrl-device.yaml] |
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properties: |
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interrupts: |
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required: true |
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pinctrl-0: |
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required: true |
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pinctrl-names: |
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required: true |
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vref-mv: |
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type: int |
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default: 3300 |
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description: The reference voltage of the ADC in mV. |
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io-channel-cells: |
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- input |
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/*
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* Copyright (c) 2025 Realtek, SIBG-SD7 |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_ADC_H |
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#define ZEPHYR_SOC_REALTEK_RTS5912_REG_ADC_H |
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struct adc_regs { |
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uint32_t ctrl; |
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uint32_t chctrl; |
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uint32_t sts; |
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uint32_t chdata[12]; |
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uint32_t coeffa; |
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uint32_t coeffb; |
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}; |
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/* CTRL */ |
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#define ADC_CTRL_EN BIT(0) |
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#define ADC_CTRL_START BIT(1) |
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#define ADC_CTRL_RST BIT(2) |
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#define ADC_CTRL_MDSEL BIT(3) |
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#define ADC_CTRL_SGLDNINTEN BIT(4) |
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#define ADC_CTRL_RPTDNINTEN BIT(5) |
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/* CHCTRL */ |
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#define ADC_CHCTRL_CH0EN BIT(0) |
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#define ADC_CHCTRL_CH1EN BIT(1) |
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#define ADC_CHCTRL_CH2EN BIT(2) |
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#define ADC_CHCTRL_CH3EN BIT(3) |
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#define ADC_CHCTRL_CH4EN BIT(4) |
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#define ADC_CHCTRL_CH5EN BIT(5) |
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#define ADC_CHCTRL_CH6EN BIT(6) |
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#define ADC_CHCTRL_CH7EN BIT(7) |
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#define ADC_CHCTRL_CH8EN BIT(8) |
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#define ADC_CHCTRL_CH9EN BIT(9) |
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#define ADC_CHCTRL_CH10EN BIT(10) |
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#define ADC_CHCTRL_CH11EN BIT(11) |
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#define ADC_CHCTRL_LPFBP BIT(12) |
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#define ADC_CHCTRL_CALBP BIT(24) |
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/* STS */ |
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#define ADC_STS_CH0DN BIT(0) |
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#define ADC_STS_CH1DN BIT(1) |
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#define ADC_STS_CH2DN BIT(2) |
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#define ADC_STS_CH3DN BIT(3) |
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#define ADC_STS_CH4DN BIT(4) |
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#define ADC_STS_CH5DN BIT(5) |
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#define ADC_STS_CH6DN BIT(6) |
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#define ADC_STS_CH7DN BIT(7) |
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#define ADC_STS_CH8DN BIT(8) |
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#define ADC_STS_CH9DN BIT(9) |
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#define ADC_STS_CH10DN BIT(10) |
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#define ADC_STS_CH11DN BIT(11) |
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#define ADC_STS_SGLDN BIT(12) |
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#define ADC_STS_RPTDN BIT(13) |
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#define ADC_STS_RDY BIT(16) |
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#define ADC_STS_LPFSTB BIT(17) |
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/* CHDATA */ |
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#define ADC_CHDATA_RESULT_Pos (0U) |
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#define ADC_CHDATA_RESULT_Msk GENMASK(11, 0) |
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#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_ADC_H */ |
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/* |
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* SPDX-License-Identifier: Apache-2.0 |
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* |
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* Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7 |
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* |
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*/ |
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/ { |
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zephyr,user { |
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io-channels = <&adc0 0>, <&adc0 1>; |
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}; |
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}; |
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&adc0 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "okay"; |
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channel@0 { |
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reg = <0>; |
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zephyr,gain = "ADC_GAIN_1"; |
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zephyr,reference = "ADC_REF_INTERNAL"; |
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zephyr,acquisition-time = <0>; |
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zephyr,resolution = <10>; |
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}; |
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channel@1 { |
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reg = <1>; |
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zephyr,gain = "ADC_GAIN_1"; |
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zephyr,reference = "ADC_REF_INTERNAL"; |
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zephyr,acquisition-time = <0>; |
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zephyr,resolution = <10>; |
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}; |
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}; |
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