zara
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

intel_adsp: Do not use hal namespace 

Do not define symbols using xtensa hal namespace.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
pull/50120/head
Flavio Ceolin 3 years ago committed by Anas Nashif
parent
b5a0567984
commit
f37e7cdd3d
4 changed files with 58 additions and 58 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 38
      soc/xtensa/intel_adsp/ace/ace-link.ld
  2. 38
      soc/xtensa/intel_adsp/cavs/linker.ld
  3. 38
      soc/xtensa/intel_adsp/common/include/adsp-vectors.h
  4. 2
      soc/xtensa/intel_adsp/common/include/cpu_init.h

38
soc/xtensa/intel_adsp/ace/ace-link.ld
Unescape View File

@ -58,61 +58,61 @@ ENTRY(rom_entry); @@ -58,61 +58,61 @@ ENTRY(rom_entry);
MEMORY {
vector_base_text :
org = XCHAL_VECBASE_RESET_PADDR_SRAM,
org = VECBASE_RESET_PADDR_SRAM,
len = MEM_VECBASE_LIT_SIZE
vector_int2_lit :
org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int2_text :
org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,
org = INTLEVEL2_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_int3_lit :
org = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int3_text :
org = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,
org = INTLEVEL3_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_int4_lit :
org = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int4_text :
org = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,
org = INTLEVEL4_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_int5_lit :
org = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int5_text :
org = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,
org = INTLEVEL5_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_int6_lit :
org = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int6_text :
org = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,
org = INTLEVEL6_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_int7_lit :
org = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int7_text :
org = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,
org = INTLEVEL7_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_kernel_lit :
org = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_kernel_text :
org = XCHAL_KERNEL_VECTOR_PADDR_SRAM,
org = KERNEL_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_user_lit :
org = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_user_text :
org = XCHAL_USER_VECTOR_PADDR_SRAM,
org = USER_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_double_lit :
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_double_text :
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,
org = DOUBLEEXC_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
imr :
org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,

38
soc/xtensa/intel_adsp/cavs/linker.ld
Unescape View File

@ -58,61 +58,61 @@ ENTRY(rom_entry); @@ -58,61 +58,61 @@ ENTRY(rom_entry);
MEMORY {
vector_base_text :
org = XCHAL_VECBASE_RESET_PADDR_SRAM,
org = VECBASE_RESET_PADDR_SRAM,
len = MEM_VECBASE_LIT_SIZE
vector_int2_lit :
org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int2_text :
org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,
org = INTLEVEL2_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_int3_lit :
org = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int3_text :
org = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,
org = INTLEVEL3_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_int4_lit :
org = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int4_text :
org = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,
org = INTLEVEL4_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_int5_lit :
org = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int5_text :
org = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,
org = INTLEVEL5_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_int6_lit :
org = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int6_text :
org = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,
org = INTLEVEL6_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_int7_lit :
org = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int7_text :
org = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,
org = INTLEVEL7_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_kernel_lit :
org = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_kernel_text :
org = XCHAL_KERNEL_VECTOR_PADDR_SRAM,
org = KERNEL_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_user_lit :
org = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_user_text :
org = XCHAL_USER_VECTOR_PADDR_SRAM,
org = USER_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
vector_double_lit :
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
org = DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_double_text :
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,
org = DOUBLEEXC_VECTOR_PADDR_SRAM,
len = MEM_VECT_TEXT_SIZE
imr :
org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,

38
soc/xtensa/intel_adsp/common/include/adsp-vectors.h
Unescape View File

@ -17,7 +17,7 @@ @@ -17,7 +17,7 @@
*/
/* This is the base address of all the vectors defined in SRAM */
#define XCHAL_VECBASE_RESET_PADDR_SRAM \
#define VECBASE_RESET_PADDR_SRAM \
(L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE)
#define MEM_VECBASE_LIT_SIZE 0x178
@ -25,32 +25,32 @@ @@ -25,32 +25,32 @@
/* The addresses of the vectors in SRAM.
* Only the memerror vector continues to point to its ROM address.
*/
#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM \
(XCHAL_VECBASE_RESET_PADDR_SRAM + 0x180)
#define INTLEVEL2_VECTOR_PADDR_SRAM \
(VECBASE_RESET_PADDR_SRAM + 0x180)
#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM \
(XCHAL_VECBASE_RESET_PADDR_SRAM + 0x1C0)
#define INTLEVEL3_VECTOR_PADDR_SRAM \
(VECBASE_RESET_PADDR_SRAM + 0x1C0)
#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM \
(XCHAL_VECBASE_RESET_PADDR_SRAM + 0x200)
#define INTLEVEL4_VECTOR_PADDR_SRAM \
(VECBASE_RESET_PADDR_SRAM + 0x200)
#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM \
(XCHAL_VECBASE_RESET_PADDR_SRAM + 0x240)
#define INTLEVEL5_VECTOR_PADDR_SRAM \
(VECBASE_RESET_PADDR_SRAM + 0x240)
#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM \
(XCHAL_VECBASE_RESET_PADDR_SRAM + 0x280)
#define INTLEVEL6_VECTOR_PADDR_SRAM \
(VECBASE_RESET_PADDR_SRAM + 0x280)
#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM \
(XCHAL_VECBASE_RESET_PADDR_SRAM + 0x2C0)
#define INTLEVEL7_VECTOR_PADDR_SRAM \
(VECBASE_RESET_PADDR_SRAM + 0x2C0)
#define XCHAL_KERNEL_VECTOR_PADDR_SRAM \
(XCHAL_VECBASE_RESET_PADDR_SRAM + 0x300)
#define KERNEL_VECTOR_PADDR_SRAM \
(VECBASE_RESET_PADDR_SRAM + 0x300)
#define XCHAL_USER_VECTOR_PADDR_SRAM \
(XCHAL_VECBASE_RESET_PADDR_SRAM + 0x340)
#define USER_VECTOR_PADDR_SRAM \
(VECBASE_RESET_PADDR_SRAM + 0x340)
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM \
(XCHAL_VECBASE_RESET_PADDR_SRAM + 0x3C0)
#define DOUBLEEXC_VECTOR_PADDR_SRAM \
(VECBASE_RESET_PADDR_SRAM + 0x3C0)
#define VECTOR_TBL_SIZE 0x0400

2
soc/xtensa/intel_adsp/common/include/cpu_init.h
Unescape View File

@ -80,7 +80,7 @@ static ALWAYS_INLINE void cpu_early_init(void) @@ -80,7 +80,7 @@ static ALWAYS_INLINE void cpu_early_init(void)
* are still disabled at this stage and will remain so
* consistently until Zephyr switches into the main thread.
*/
reg = XCHAL_VECBASE_RESET_PADDR_SRAM;
reg = VECBASE_RESET_PADDR_SRAM;
__asm__ volatile("wsr %0, VECBASE" :: "r"(reg));
}

Write Preview
Loading…
Cancel
Save