Browse Source
Create common source code to use for supporting HyperFlash. Rename 'FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME' to 'FLASH_NXP_S32_QSPI_SFDP_RUNTIME' as a common kconfig. Add the 'max-program-buffer-size' property to use for setting memory pageSize, instead of using 'CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE' for setting. Add the 'write-block-size' propertyto use for setting the number of bytes used in write operations, it also uses to instead of the 'memory-alignment' property. Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>pull/84302/head
Cong Nguyen Huu
10 months ago
committed by
Benjamin Cabé
8 changed files with 420 additions and 355 deletions
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/*
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* Copyright 2023-2024 NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/kernel.h> |
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#include <zephyr/drivers/flash.h> |
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#include <zephyr/logging/log.h> |
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#include <Qspi_Ip.h> |
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#include "flash_nxp_s32_qspi.h" |
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LOG_MODULE_REGISTER(flash_nxp_s32_qspi, CONFIG_FLASH_LOG_LEVEL); |
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static ALWAYS_INLINE bool area_is_subregion(const struct device *dev, off_t offset, size_t size) |
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{ |
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Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev); |
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return ((offset >= 0) && (offset < memory_cfg->memSize) && |
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((memory_cfg->memSize - offset) >= size)); |
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} |
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uint8_t nxp_s32_qspi_register_device(void) |
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{ |
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static uint8_t instance_cnt; |
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return instance_cnt++; |
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} |
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/* Must be called with lock */ |
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int nxp_s32_qspi_wait_until_ready(const struct device *dev) |
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{ |
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struct nxp_s32_qspi_data *data = dev->data; |
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Qspi_Ip_StatusType status; |
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uint32_t timeout = 0xFFFFFF; |
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int ret = 0; |
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do { |
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status = Qspi_Ip_GetMemoryStatus(data->instance); |
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timeout--; |
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} while ((status == STATUS_QSPI_IP_BUSY) && (timeout > 0)); |
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if (status != STATUS_QSPI_IP_SUCCESS) { |
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LOG_ERR("Failed to read memory status (%d)", status); |
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ret = -EIO; |
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} else if (timeout == 0) { |
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LOG_ERR("Timeout, memory is busy"); |
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ret = -ETIMEDOUT; |
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} |
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return ret; |
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} |
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int nxp_s32_qspi_read(const struct device *dev, off_t offset, void *dest, size_t size) |
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{ |
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struct nxp_s32_qspi_data *data = dev->data; |
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Qspi_Ip_StatusType status; |
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int ret = 0; |
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if (!dest) { |
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return -EINVAL; |
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} |
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if (!area_is_subregion(dev, offset, size)) { |
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return -EINVAL; |
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} |
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if (size) { |
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nxp_s32_qspi_lock(dev); |
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status = Qspi_Ip_Read(data->instance, (uint32_t)offset, (uint8_t *)dest, |
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(uint32_t)size); |
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if (status != STATUS_QSPI_IP_SUCCESS) { |
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LOG_ERR("Failed to read %zu bytes at 0x%lx (%d)", size, offset, status); |
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ret = -EIO; |
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} |
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nxp_s32_qspi_unlock(dev); |
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} |
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return ret; |
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} |
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int nxp_s32_qspi_write(const struct device *dev, off_t offset, const void *src, size_t size) |
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{ |
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const struct nxp_s32_qspi_config *config = dev->config; |
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struct nxp_s32_qspi_data *data = dev->data; |
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Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev); |
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Qspi_Ip_StatusType status; |
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size_t max_write = (size_t)MIN(QSPI_IP_MAX_WRITE_SIZE, memory_cfg->pageSize); |
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size_t len; |
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int ret = 0; |
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if (!src || !size) { |
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return -EINVAL; |
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} |
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if (!area_is_subregion(dev, offset, size) || |
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(offset % config->flash_parameters.write_block_size) || |
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(size % config->flash_parameters.write_block_size)) { |
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return -EINVAL; |
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} |
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nxp_s32_qspi_lock(dev); |
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while (size) { |
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len = MIN(max_write - (offset % max_write), size); |
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status = Qspi_Ip_Program(data->instance, (uint32_t)offset, (const uint8_t *)src, |
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(uint32_t)len); |
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if (status != STATUS_QSPI_IP_SUCCESS) { |
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LOG_ERR("Failed to write %zu bytes at 0x%lx (%d)", len, offset, status); |
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ret = -EIO; |
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break; |
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} |
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ret = nxp_s32_qspi_wait_until_ready(dev); |
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if (ret != 0) { |
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break; |
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} |
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if (IS_ENABLED(CONFIG_FLASH_NXP_S32_QSPI_VERIFY_WRITE)) { |
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status = Qspi_Ip_ProgramVerify(data->instance, (uint32_t)offset, |
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(const uint8_t *)src, (uint32_t)len); |
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if (status != STATUS_QSPI_IP_SUCCESS) { |
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LOG_ERR("Write verification failed at 0x%lx (%d)", offset, status); |
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ret = -EIO; |
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break; |
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} |
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} |
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size -= len; |
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src = (const uint8_t *)src + len; |
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offset += len; |
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} |
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nxp_s32_qspi_unlock(dev); |
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return ret; |
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} |
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static int nxp_s32_qspi_erase_block(const struct device *dev, off_t offset, size_t size, |
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size_t *erase_size) |
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{ |
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struct nxp_s32_qspi_data *data = dev->data; |
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Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev); |
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Qspi_Ip_EraseVarConfigType *etp = NULL; |
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Qspi_Ip_EraseVarConfigType *etp_tmp; |
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Qspi_Ip_StatusType status; |
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int ret = 0; |
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/*
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* Find the erase type with bigger size that can erase all or part of the |
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* requested memory size |
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*/ |
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for (uint8_t i = 0; i < QSPI_IP_ERASE_TYPES; i++) { |
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etp_tmp = (Qspi_Ip_EraseVarConfigType *)&(memory_cfg->eraseSettings.eraseTypes[i]); |
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if ((etp_tmp->eraseLut != QSPI_IP_LUT_INVALID) && |
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QSPI_IS_ALIGNED(offset, etp_tmp->size) && (BIT(etp_tmp->size) <= size) && |
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((etp == NULL) || (etp_tmp->size > etp->size))) { |
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etp = etp_tmp; |
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} |
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} |
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if (etp != NULL) { |
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*erase_size = BIT(etp->size); |
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status = Qspi_Ip_EraseBlock(data->instance, (uint32_t)offset, *erase_size); |
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if (status != STATUS_QSPI_IP_SUCCESS) { |
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LOG_ERR("Failed to erase %zu bytes at 0x%lx (%d)", *erase_size, |
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(long)offset, status); |
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ret = -EIO; |
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} |
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} else { |
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LOG_ERR("Can't find erase size to erase %zu bytes", size); |
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ret = -EINVAL; |
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} |
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return ret; |
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} |
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int nxp_s32_qspi_erase(const struct device *dev, off_t offset, size_t size) |
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{ |
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struct nxp_s32_qspi_data *data = dev->data; |
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Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev); |
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Qspi_Ip_StatusType status; |
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size_t erase_size; |
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int ret = 0; |
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if (!area_is_subregion(dev, offset, size) || !size) { |
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return -EINVAL; |
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} |
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nxp_s32_qspi_lock(dev); |
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if (size == memory_cfg->memSize) { |
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status = Qspi_Ip_EraseChip(data->instance); |
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if (status != STATUS_QSPI_IP_SUCCESS) { |
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LOG_ERR("Failed to erase chip (%d)", status); |
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ret = -EIO; |
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} |
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} else { |
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while (size > 0) { |
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erase_size = 0; |
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ret = nxp_s32_qspi_erase_block(dev, offset, size, &erase_size); |
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if (ret != 0) { |
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break; |
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} |
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ret = nxp_s32_qspi_wait_until_ready(dev); |
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if (ret != 0) { |
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break; |
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} |
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if (IS_ENABLED(CONFIG_FLASH_NXP_S32_QSPI_VERIFY_ERASE)) { |
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status = Qspi_Ip_EraseVerify(data->instance, (uint32_t)offset, |
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erase_size); |
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if (status != STATUS_QSPI_IP_SUCCESS) { |
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LOG_ERR("Erase verification failed at 0x%lx (%d)", offset, |
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status); |
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ret = -EIO; |
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break; |
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} |
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} |
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offset += erase_size; |
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size -= erase_size; |
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} |
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} |
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nxp_s32_qspi_unlock(dev); |
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return ret; |
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} |
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const struct flash_parameters *nxp_s32_qspi_get_parameters(const struct device *dev) |
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{ |
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const struct nxp_s32_qspi_config *config = dev->config; |
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return &config->flash_parameters; |
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} |
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#if defined(CONFIG_FLASH_PAGE_LAYOUT) |
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void nxp_s32_qspi_pages_layout(const struct device *dev, const struct flash_pages_layout **layout, |
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size_t *layout_size) |
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{ |
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const struct nxp_s32_qspi_config *config = dev->config; |
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*layout = &config->layout; |
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*layout_size = 1; |
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} |
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */ |
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#if defined(CONFIG_FLASH_JESD216_API) || !defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME) |
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int nxp_s32_qspi_read_id(const struct device *dev, uint8_t *id) |
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{ |
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struct nxp_s32_qspi_data *data = dev->data; |
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Qspi_Ip_StatusType status; |
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int ret = 0; |
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nxp_s32_qspi_lock(dev); |
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status = Qspi_Ip_ReadId(data->instance, id); |
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if (status != STATUS_QSPI_IP_SUCCESS) { |
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LOG_ERR("Failed to read device ID (%d)", status); |
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ret = -EIO; |
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} |
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nxp_s32_qspi_unlock(dev); |
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return ret; |
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} |
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#endif /* CONFIG_FLASH_JESD216_API || !CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME */ |
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@@ -0,0 +1,111 @@
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/*
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* Copyright 2023-2024 NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_DRIVERS_FLASH_NXP_S32_QSPI_H_ |
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#define ZEPHYR_DRIVERS_FLASH_NXP_S32_QSPI_H_ |
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#include "jesd216.h" |
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#define QSPI_ERASE_VALUE 0xff |
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#define QSPI_IS_ALIGNED(addr, bits) (((addr) & BIT_MASK(bits)) == 0) |
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#if defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME) |
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/* Size of LUT */ |
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#define QSPI_SFDP_LUT_SIZE 130U |
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/* Size of init operations */ |
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#define QSPI_SFDP_INIT_OP_SIZE 8U |
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#if defined(CONFIG_FLASH_JESD216_API) |
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/* Size of all LUT sequences for JESD216 operations */ |
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#define QSPI_JESD216_SEQ_SIZE 8U |
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#endif /* CONFIG_FLASH_JESD216_API */ |
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#endif /* CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME */ |
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struct nxp_s32_qspi_config { |
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const struct device *controller; |
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struct flash_parameters flash_parameters; |
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#if defined(CONFIG_FLASH_PAGE_LAYOUT) |
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struct flash_pages_layout layout; |
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#endif |
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#if !defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME) |
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const Qspi_Ip_MemoryConfigType memory_cfg; |
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enum jesd216_dw15_qer_type qer_type; |
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bool quad_mode; |
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#endif |
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}; |
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struct nxp_s32_qspi_data { |
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uint8_t instance; |
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Qspi_Ip_MemoryConnectionType memory_conn_cfg; |
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uint8_t read_sfdp_lut_idx; |
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#if defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME) |
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Qspi_Ip_MemoryConfigType memory_cfg; |
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Qspi_Ip_InstrOpType lut_ops[QSPI_SFDP_LUT_SIZE]; |
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Qspi_Ip_InitOperationType init_ops[QSPI_SFDP_INIT_OP_SIZE]; |
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#endif |
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#if defined(CONFIG_MULTITHREADING) |
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struct k_sem sem; |
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#endif |
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}; |
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static ALWAYS_INLINE Qspi_Ip_MemoryConfigType *get_memory_config(const struct device *dev) |
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{ |
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#if defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME) |
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return &((struct nxp_s32_qspi_data *)dev->data)->memory_cfg; |
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#else |
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return ((Qspi_Ip_MemoryConfigType *)&((const struct nxp_s32_qspi_config *)dev->config) |
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->memory_cfg); |
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#endif |
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} |
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static inline void nxp_s32_qspi_lock(const struct device *dev) |
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{ |
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#ifdef CONFIG_MULTITHREADING |
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struct nxp_s32_qspi_data *data = dev->data; |
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k_sem_take(&data->sem, K_FOREVER); |
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#else |
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ARG_UNUSED(dev); |
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#endif |
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} |
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static inline void nxp_s32_qspi_unlock(const struct device *dev) |
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{ |
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#ifdef CONFIG_MULTITHREADING |
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struct nxp_s32_qspi_data *data = dev->data; |
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k_sem_give(&data->sem); |
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#else |
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ARG_UNUSED(dev); |
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#endif |
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} |
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/*
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* This function retrieves the device instance used by the HAL |
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* to access the internal driver state. |
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*/ |
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uint8_t nxp_s32_qspi_register_device(void); |
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int nxp_s32_qspi_wait_until_ready(const struct device *dev); |
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int nxp_s32_qspi_read(const struct device *dev, off_t offset, void *dest, size_t size); |
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int nxp_s32_qspi_write(const struct device *dev, off_t offset, const void *src, size_t size); |
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int nxp_s32_qspi_erase(const struct device *dev, off_t offset, size_t size); |
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const struct flash_parameters *nxp_s32_qspi_get_parameters(const struct device *dev); |
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#if defined(CONFIG_FLASH_PAGE_LAYOUT) |
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void nxp_s32_qspi_pages_layout(const struct device *dev, const struct flash_pages_layout **layout, |
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size_t *layout_size); |
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */ |
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#if defined(CONFIG_FLASH_JESD216_API) || !defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME) |
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int nxp_s32_qspi_read_id(const struct device *dev, uint8_t *id); |
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#endif /* CONFIG_FLASH_JESD216_API || !CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME */ |
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#endif /* ZEPHYR_DRIVERS_FLASH_NXP_S32_QSPI_H_ */ |
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