drivers: memc: enable support for SDRAM controller on Renesas RA family

First commit to add support for SDRAM controller on Renesas RA SoC

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>

drivers/memc/CMakeLists.txt

@@ -14,6 +14,7 @@ zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_APS6408L memc_mcux_flexspi
 zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_APS6404L memc_mcux_flexspi_aps6404l.c)
 zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_IS66WVQ8M4 memc_mcux_flexspi_is66wvq8m4.c)
 zephyr_library_sources_ifdef(CONFIG_MEMC_NXP_FLEXRAM memc_nxp_flexram.c)
+zephyr_library_sources_ifdef(CONFIG_MEMC_RENESAS_RA_SDRAM memc_renesas_ra_sdram.c)
 
 zephyr_library_sources_ifdef(CONFIG_MEMC_SAM_SMC memc_sam_smc.c)
 

drivers/memc/Kconfig

@@ -32,6 +32,8 @@ source "drivers/memc/Kconfig.smartbond"
 
 source "drivers/memc/Kconfig.mspi"
 
+source "drivers/memc/Kconfig.renesas_ra"
+
 module = MEMC
 module-str = memc
 source "subsys/logging/Kconfig.template.log_config"

drivers/memc/Kconfig.renesas_ra

@@ -0,0 +1,12 @@
+# Renesas RA Family
+
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config MEMC_RENESAS_RA_SDRAM
+	bool "Renesas RA sdram controller"
+	default y
+	depends on DT_HAS_RENESAS_RA_SDRAM_ENABLED
+	select USE_RA_FSP_SDRAM
+	help
+	  Enable Renesas RA sdram controller

drivers/memc/memc_renesas_ra_sdram.c

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_ra_sdram
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(memc_renesas_ra_sdram, CONFIG_MEMC_LOG_LEVEL);
+
+struct memc_renesas_ra_sdram_config {
+	const struct pinctrl_dev_config *pincfg;
+};
+
+static int renesas_ra_sdram_init(const struct device *dev)
+{
+	const struct memc_renesas_ra_sdram_config *config = dev->config;
+	int err;
+
+	err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
+	if (err) {
+		LOG_ERR("pin function initial failed");
+		return err;
+	}
+
+	R_BSP_SdramInit(true);
+
+	return 0;
+}
+
+PINCTRL_DT_INST_DEFINE(0);
+static const struct memc_renesas_ra_sdram_config config = {
+	.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
+};
+
+DEVICE_DT_INST_DEFINE(0, renesas_ra_sdram_init, NULL, NULL, &config, POST_KERNEL,
+		      CONFIG_MEMC_INIT_PRIORITY, NULL);

dts/bindings/memory-controllers/renesas,ra-sdram.yaml

@@ -0,0 +1,130 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Renesas RA SDRAM controller.
+  sdram {
+      pinctrl-0 = <&sdram_default>;
+      pinctrl-names = "default";
+      status = "okay";
+      auto-refresh-interval = <10>;
+      auto-refresh-count = <8>;
+      precharge-cycle-count = <3>;
+      multiplex-addr-shift = "10-bit";
+      edian-mode = "little-endian";
+      continuous-access;
+      bus-width = "16-bit";
+      bank@0 {
+        reg = <0>;
+        renesas,ra-sdram-timing = <RENESAS_RA_SDRAM_TRAS_6CYCLES
+                  RENESAS_RA_SDRAM_TRCD_3CYCLES
+                  RENESAS_RA_SDRAM_TRP_3CYCLES
+                  RENESAS_RA_SDRAM_TWR_2CYCLES
+                  RENESAS_RA_SDRAM_TCL_3CYCLES
+                  937
+                  RENESAS_RA_SDRAM_TREFW_8CYCLES>;
+      };
+
+  Note that you will find definitions for the renesas,ra-sdram-control field at
+  dt-bindings/memory-controller/renesas,ra-sdram.h. This file is already included
+  in the SoC DeviceTree files.
+
+  Finally, in order to make the memory available you will need to define new
+  memory device/s in DeviceTree:
+
+  sdram1: sdram@68000000 {
+      compatible = "zephyr,memory-region", "mmio-sram";
+      device_type = "memory";
+      reg = <0x68000000 DT_SIZE_M(X)>;
+      zephyr,memory-region = "SDRAM";
+  };
+
+compatible: "renesas,ra-sdram"
+
+include: [base.yaml, pinctrl-device.yaml]
+
+properties:
+  "#address-cells":
+    required: true
+    const: 1
+
+  "#size-cells":
+    required: true
+    const: 0
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  auto-refresh-interval:
+    type: int
+    default: 10
+    description: Number of auto-refresh-interval.
+
+  auto-refresh-count:
+    type: int
+    default: 8
+    description: Number of auto-refresh-count.
+
+  precharge-cycle-count:
+    type: int
+    default: 3
+    description: Number of precharge-cycle-count.
+
+  multiplex-addr-shift:
+    type: string
+    default: "10-bit"
+    enum:
+      - "8-bit"
+      - "9-bit"
+      - "10-bit"
+      - "11-bit"
+    description: |
+      Select the size of the shift towards the lower half of the row address in row address/column
+      address multiplexing.
+
+  edian-mode:
+    type: string
+    default: "little-endian"
+    enum:
+      - "little-endian"
+      - "big-endian"
+    description: Specifies the endianness for the SDRAM address space.
+
+  continuous-access:
+    type: boolean
+    description: Enables or disables continuous access to the SDRAM access space.
+
+  bus-width:
+    type: string
+    default: "16-bit"
+    enum:
+      - "16-bit"
+      - "32-bit"
+      - "8-bit"
+    description: Specify the data bus width for SDRAM
+
+child-binding:
+  description: SDRAM bank.
+
+  properties:
+    reg:
+      type: int
+      required: true
+
+    renesas,ra-sdram-timing:
+      type: array
+      required: true
+      description: |
+        SDRAM timing configuration. Expected fields, in order, are,
+
+        - TRAS: Row active interval. The effective value from 1 to 7 cycles
+        - TRCD: Row column latency. The effective value from 1 to 4 cycles
+        - TRP: Row precharge interval. The effective value from 1 to 8 cycles
+        - TWR: Write recovery interval. The effective value from 1 to 2 cycles
+        - TCL: Column latency. The effective value from 1 to 3 cycles
+        - TRFC: Auto-Refresh Request Interval Setting.
+        - TREFW: Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting.
+          The effective value from 1 to 16 cycles

include/zephyr/dt-bindings/memory-controller/renesas,ra-sdram.h

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_RENESAS_RA_SDRAM_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_RENESAS_RA_SDRAM_H_
+
+#define SDRAM_TRAS_1CYCLES (1)
+#define SDRAM_TRAS_2CYCLES (2)
+#define SDRAM_TRAS_3CYCLES (3)
+#define SDRAM_TRAS_4CYCLES (4)
+#define SDRAM_TRAS_5CYCLES (5)
+#define SDRAM_TRAS_6CYCLES (6)
+#define SDRAM_TRAS_7CYCLES (7)
+
+#define SDRAM_TRCD_1CYCLES (1)
+#define SDRAM_TRCD_2CYCLES (2)
+#define SDRAM_TRCD_3CYCLES (3)
+#define SDRAM_TRCD_4CYCLES (4)
+
+#define SDRAM_TRP_1CYCLES (1)
+#define SDRAM_TRP_2CYCLES (2)
+#define SDRAM_TRP_3CYCLES (3)
+#define SDRAM_TRP_4CYCLES (4)
+#define SDRAM_TRP_5CYCLES (5)
+#define SDRAM_TRP_6CYCLES (6)
+#define SDRAM_TRP_7CYCLES (7)
+#define SDRAM_TRP_8CYCLES (8)
+
+#define SDRAM_TWR_1CYCLES (1)
+#define SDRAM_TWR_2CYCLES (2)
+
+#define SDRAM_TCL_1CYCLES (1)
+#define SDRAM_TCL_2CYCLES (2)
+#define SDRAM_TCL_3CYCLES (3)
+
+#define SDRAM_TREFW_1CYCLES  (1)
+#define SDRAM_TREFW_2CYCLES  (2)
+#define SDRAM_TREFW_3CYCLES  (3)
+#define SDRAM_TREFW_4CYCLES  (4)
+#define SDRAM_TREFW_5CYCLES  (5)
+#define SDRAM_TREFW_6CYCLES  (6)
+#define SDRAM_TREFW_7CYCLES  (7)
+#define SDRAM_TREFW_8CYCLES  (8)
+#define SDRAM_TREFW_9CYCLES  (9)
+#define SDRAM_TREFW_10CYCLES (10)
+#define SDRAM_TREFW_11CYCLES (11)
+#define SDRAM_TREFW_12CYCLES (12)
+#define SDRAM_TREFW_13CYCLES (13)
+#define SDRAM_TREFW_14CYCLES (14)
+#define SDRAM_TREFW_15CYCLES (15)
+#define SDRAM_TREFW_16CYCLES (16)
+
+#define SDRAM_AUTO_REFREDSH_INTERVEL_3CYCLES  (3)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_4CYCLES  (4)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_5CYCLES  (5)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_6CYCLES  (6)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_7CYCLES  (7)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_8CYCLES  (8)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_9CYCLES  (9)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_10CYCLES (10)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_11CYCLES (11)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_12CYCLES (12)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_13CYCLES (13)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_14CYCLES (14)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_15CYCLES (15)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_16CYCLES (16)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_17CYCLES (17)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_18CYCLES (18)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_19CYCLES (19)
+#define SDRAM_AUTO_REFREDSH_INTERVEL_20CYCLES (20)
+
+#define SDRAM_AUTO_REFREDSH_COUNT_1TIMES  (1)
+#define SDRAM_AUTO_REFREDSH_COUNT_2TIMES  (2)
+#define SDRAM_AUTO_REFREDSH_COUNT_3TIMES  (3)
+#define SDRAM_AUTO_REFREDSH_COUNT_4TIMES  (4)
+#define SDRAM_AUTO_REFREDSH_COUNT_5TIMES  (5)
+#define SDRAM_AUTO_REFREDSH_COUNT_6TIMES  (6)
+#define SDRAM_AUTO_REFREDSH_COUNT_7TIMES  (7)
+#define SDRAM_AUTO_REFREDSH_COUNT_8TIMES  (8)
+#define SDRAM_AUTO_REFREDSH_COUNT_9TIMES  (9)
+#define SDRAM_AUTO_REFREDSH_COUNT_10TIMES (10)
+#define SDRAM_AUTO_REFREDSH_COUNT_11TIMES (11)
+#define SDRAM_AUTO_REFREDSH_COUNT_12TIMES (12)
+#define SDRAM_AUTO_REFREDSH_COUNT_13TIMES (13)
+#define SDRAM_AUTO_REFREDSH_COUNT_14TIMES (14)
+#define SDRAM_AUTO_REFREDSH_COUNT_15TIMES (15)
+
+#define SDRAM_AUTO_PRECHARGE_CYCLE_3CYCLES  (3)
+#define SDRAM_AUTO_PRECHARGE_CYCLE_4CYCLES  (4)
+#define SDRAM_AUTO_PRECHARGE_CYCLE_5CYCLES  (5)
+#define SDRAM_AUTO_PRECHARGE_CYCLE_6CYCLES  (6)
+#define SDRAM_AUTO_PRECHARGE_CYCLE_7CYCLES  (7)
+#define SDRAM_AUTO_PRECHARGE_CYCLE_8CYCLES  (8)
+#define SDRAM_AUTO_PRECHARGE_CYCLE_9CYCLES  (9)
+#define SDRAM_AUTO_PRECHARGE_CYCLE_10CYCLES (10)
+
+#endif

modules/Kconfig.renesas_fsp

@@ -115,6 +115,11 @@ config USE_RA_FSP_USB_DEVICE
 	help
 	  Enable RA FSP USB Device Controller driver
 
+config USE_RA_FSP_SDRAM
+	bool
+	help
+	  Enable RA FSP SDRAM support
+
 endif # HAS_RENESAS_RA_FSP
 
 if HAS_RENESAS_RZ_FSP