diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c
index 4ed253587ca..c58df7ec8a6 100644
--- a/drivers/clock_control/clock_stm32_ll_h7.c
+++ b/drivers/clock_control/clock_stm32_ll_h7.c
@@ -32,6 +32,7 @@
 /**
  * @brief fill in AHB/APB buses configuration structure
  */
+#if !defined(CONFIG_CPU_CORTEX_M4)
 static void config_bus_prescalers(void)
 {
 	LL_RCC_SetSysPrescaler(sysclk_prescaler(CONFIG_CLOCK_STM32_D1CPRE));
@@ -41,6 +42,7 @@ static void config_bus_prescalers(void)
 	LL_RCC_SetAPB3Prescaler(apb3_prescaler(CONFIG_CLOCK_STM32_D1PPRE));
 	LL_RCC_SetAPB4Prescaler(apb4_prescaler(CONFIG_CLOCK_STM32_D3PPRE));
 }
+#endif /* CONFIG_CPU_CORTEX_M4 */
 
 static u32_t get_bus_clock(u32_t clock, u32_t prescaler)
 {
@@ -54,6 +56,9 @@ static inline int stm32_clock_control_on(struct device *dev,
 
 	ARG_UNUSED(dev);
 
+	/* Both cores can access bansk by following LL API */
+	/* Using "_Cn_" LL API would restrict access to one or the other */
+
 	switch (pclken->bus) {
 	case STM32_CLOCK_BUS_AHB1:
 		LL_AHB1_GRP1_EnableClock(pclken->enr);
@@ -96,6 +101,9 @@ static inline int stm32_clock_control_off(struct device *dev,
 
 	ARG_UNUSED(dev);
 
+	/* Both cores can access bansk by following LL API */
+	/* Using "_Cn_" LL API would restrict access to one or the other */
+
 	switch (pclken->bus) {
 	case STM32_CLOCK_BUS_AHB1:
 		LL_AHB1_GRP1_DisableClock(pclken->enr);
@@ -194,6 +202,8 @@ static int stm32_clock_control_init(struct device *dev)
 {
 	ARG_UNUSED(dev);
 
+#if !defined(CONFIG_CPU_CORTEX_M4)
+
 #ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
 	/* Power Configuration */
 	LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
@@ -252,6 +262,8 @@ static int stm32_clock_control_init(struct device *dev)
 	#error "CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL not selected"
 #endif /* CLOCK_STM32_SYSCLK_SRC_PLL */
 
+#endif /* CONFIG_CPU_CORTEX_M4 */
+
 	/* Set systick to 1ms */
 	SysTick_Config(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000);
 	/* Update CMSIS variable */