boards: nxp: s32z2xxdc2: convert to hwmv2

Convert `s32z270dc2` boards to hardware model v2. The board has been
renamed to `s32z2xxdc2` to be able to support in the future other
SoCs from this series that can also work on this board.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>

boards/boards_legacy/arm/s32z270dc2_r52/Kconfig.board

@@ -1,12 +0,0 @@
-# Copyright 2022 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_S32Z270DC2_RTU0_R52
-	bool "NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores"
-	depends on SOC_SERIES_S32ZE_R52
-	select SOC_PART_NUMBER_S32Z27
-
-config BOARD_S32Z270DC2_RTU1_R52
-	bool "NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores"
-	depends on SOC_SERIES_S32ZE_R52
-	select SOC_PART_NUMBER_S32Z27

boards/boards_legacy/arm/s32z270dc2_r52/Kconfig.defconfig

@@ -1,34 +0,0 @@
-# Copyright 2022 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-if BOARD_S32Z270DC2_RTU0_R52 || BOARD_S32Z270DC2_RTU1_R52
-
-config BUILD_OUTPUT_BIN
-	default n
-
-config BOARD
-	default "s32z270dc2_rtu0_r52" if BOARD_S32Z270DC2_RTU0_R52
-	default "s32z270dc2_rtu1_r52" if BOARD_S32Z270DC2_RTU1_R52
-
-config NXP_S32_RTU_INDEX
-	default 0 if BOARD_S32Z270DC2_RTU0_R52
-	default 1 if BOARD_S32Z270DC2_RTU1_R52
-
-if SERIAL
-
-config UART_INTERRUPT_DRIVEN
-	default y
-
-config UART_CONSOLE
-	default y
-
-endif # SERIAL
-
-if SHELL
-
-config SHELL_STACK_SIZE
-	default 4096
-
-endif # SHELL
-
-endif # BOARD_S32Z270DC2_RTU0_R52 || BOARD_S32Z270DC2_RTU1_R52

boards/boards_legacy/arm/s32z270dc2_r52/revision.cmake

@@ -1,8 +0,0 @@
-# Copyright 2023 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-board_check_revision(
-  FORMAT LETTER
-  DEFAULT_REVISION B
-  VALID_REVISIONS B D
-)

boards/nxp/s32z2xxdc2/Kconfig.defconfig

@@ -0,0 +1,26 @@
+# Copyright 2022,2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1
+
+config BUILD_OUTPUT_BIN
+	default n
+
+if SERIAL
+
+config UART_INTERRUPT_DRIVEN
+	default y
+
+config UART_CONSOLE
+	default y
+
+endif # SERIAL
+
+if SHELL
+
+config SHELL_STACK_SIZE
+	default 4096
+
+endif # SHELL
+
+endif # BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1

boards/nxp/s32z2xxdc2/Kconfig.s32z2xxdc2

@@ -0,0 +1,7 @@
+# Copyright 2022,2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_S32Z2XXDC2
+	select SOC_S32Z270_RTU0 if BOARD_S32Z2XXDC2_S32Z270_RTU0
+	select SOC_S32Z270_RTU1 if BOARD_S32Z2XXDC2_S32Z270_RTU1
+	select SOC_PART_NUMBER_P32Z270ADCK0MJFT if BOARD_S32Z2XXDC2

boards/nxp/s32z2xxdc2/board.yml

@@ -0,0 +1,11 @@
+board:
+  name: s32z2xxdc2
+  vendor: nxp
+  revision:
+    format: letter
+    default: B
+    revisions:
+      - name: B
+      - name: D
+  socs:
+    - name: s32z270

boards/nxp/s32z2xxdc2/doc/index.rst

@@ -1,4 +1,4 @@
-.. _s32z270dc2_r52:
+.. _s32z2xxdc2:
 
 NXP X-S32Z27X-DC (DC2)
 ######################
@@ -6,14 +6,14 @@ NXP X-S32Z27X-DC (DC2)
 Overview
 ********
 
-The X-S32Z27X-DC (DC2) board is based on the NXP S32Z270 Real-Time Processor,
+The X-S32Z27X-DC (DC2) board is based on the NXP S32Z2 Real-Time Processor,
 which includes two Real-Time Units (RTU) composed of four ARM Cortex-R52 cores
 each, with flexible split/lock configurations.
 
-There is one Zephyr board per RTU:
+There is one Zephyr board per SoC/RTU:
 
-- ``s32z270dc2_rtu0_r52``, for RTU0
+- ``s32z2xxdc2/s32z270/rtu0``, for S32Z270/RTU0
-- ``s32z270dc2_rtu1_r52``, for RTU1.
+- ``s32z2xxdc2/s32z270/rtu1``, for S32Z270/RTU1.
 
 Hardware
 ********
@@ -142,8 +142,8 @@ not supported as this feature is not available on NXP S32 CANXL HAL.
 Programming and Debugging
 *************************
 
-Applications for the ``s32z270dc2_rtu0_r52`` and ``s32z270dc2_rtu1_r52`` boards
+Applications for the ``s32z2xxdc2`` boards can be built in the usual way as
-can be built in the usual way as documented in :ref:`build_an_application`.
+documented in :ref:`build_an_application`.
 
 Currently is only possible to load and execute a Zephyr application binary on
 this board from the core internal SRAM.
@@ -177,11 +177,11 @@ Debugging
 =========
 
 You can build and debug the :ref:`hello_world` sample for the board
-``s32z270dc2_rtu0_r52`` with:
+``s32z2xxdc2/s32z270/rtu0`` with:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: s32z270dc2_rtu0_r52
+   :board: s32z2xxdc2/s32z270/rtu0
    :goals: build debug
 
 In case you are using a newer PCB revision, you have to use an adapted board
@@ -189,7 +189,7 @@ definition as the default PCB revision is B. For example, if using revision D:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: s32z270dc2_rtu0_r52@D
+   :board: s32z2xxdc2@D/s32z270/rtu0
    :goals: build debug
    :compact:
 
@@ -199,13 +199,13 @@ the terminal:
 
 .. code-block:: console
 
-   Hello World! s32z270dc2_rtu0_r52
+   Hello World! s32z2xxdc2
 
 To debug with Lauterbach TRACE32 softare run instead:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: s32z270dc2_rtu0_r52
+   :board: s32z2xxdc2/s32z270/rtu0
    :goals: build debug -r trace32
    :compact:
 
@@ -219,7 +219,7 @@ SRAM and run.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: s32z270dc2_rtu0_r52
+   :board: s32z2xxdc2/s32z270/rtu0
    :goals: build flash -r trace32
    :compact:
 
@@ -234,7 +234,7 @@ To imitate a similar behavior using NXP S32 Debug Probe runner, you can run the
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: s32z270dc2_rtu0_r52
+   :board: s32z2xxdc2/s32z270/rtu0
    :goals: build debug --tool-opt='--batch'
    :compact:
 
@@ -268,17 +268,16 @@ the build configuration. To debug for a core different than the default use:
 
 Where:
 
-- ``<rtu_id>`` is the zero-based RTU index (0 for ``s32z270dc2_rtu0_r52``
+- ``<rtu_id>`` is the zero-based RTU index
-  and 1 for ``s32z270dc2_rtu1_r52``)
 - ``<core_id>`` is the zero-based core index relative to the RTU on which to
   run the Zephyr application (0, 1, 2 or 3)
 
 For example, to build the :ref:`hello_world` sample for the board
-``s32z270dc2_rtu0_r52`` with split-lock core configuration:
+``s32z2xxdc2/s32z270/rtu0`` with split-lock core configuration:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: s32z270dc2_rtu0_r52
+   :board: s32z2xxdc2/s32z270/rtu0
    :goals: build
    :gen-args: -DCONFIG_DCLS=n
    :compact:

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi

@@ -1,10 +1,10 @@
 /*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "s32z270dc2_r52-pinctrl-common.dtsi"
+#include "s32z2xxdc2_s32z270_pinctrl.dtsi"
 
 &swt0 {
 	status = "okay";

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts

@@ -1,12 +1,12 @@
 /*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 /dts-v1/;
 #include <arm/nxp/nxp_s32z27x_rtu0_r52.dtsi>
-#include "s32z270dc2_r52.dtsi"
+#include "s32z2xxdc2_s32z270.dtsi"
 
 / {
 	model = "NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores";

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml

@@ -1,7 +1,7 @@
-# Copyright 2022-2023 NXP
+# Copyright 2022-2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-identifier: s32z270dc2_rtu0_r52
+identifier: s32z2xxdc2/s32z270/rtu0
 name: NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores
 type: mcu
 arch: arm

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml

@@ -1,7 +1,7 @@
-# Copyright 2023 NXP
+# Copyright 2023-2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-identifier: s32z270dc2_rtu0_r52@D
+identifier: s32z2xxdc2@D/s32z270/rtu0
 name: NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores (rev. D)
 type: mcu
 arch: arm

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig

@@ -1,9 +1,6 @@
-# Copyright 2022 NXP
+# Copyright 2022,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_BOARD_S32Z270DC2_RTU0_R52=y
-CONFIG_SOC_SERIES_S32ZE_R52=y
-CONFIG_SOC_S32Z27_R52=y
 CONFIG_XIP=n
 CONFIG_ISR_STACK_SIZE=512
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts

@@ -1,12 +1,12 @@
 /*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 /dts-v1/;
 #include <arm/nxp/nxp_s32z27x_rtu1_r52.dtsi>
-#include "s32z270dc2_r52.dtsi"
+#include "s32z2xxdc2_s32z270.dtsi"
 
 / {
 	model = "NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores";

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml

@@ -1,7 +1,7 @@
-# Copyright 2022-2023 NXP
+# Copyright 2022-2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-identifier: s32z270dc2_rtu1_r52
+identifier: s32z2xxdc2/s32z270/rtu1
 name: NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores
 type: mcu
 arch: arm

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml

@@ -1,7 +1,7 @@
-# Copyright 2022-2023 NXP
+# Copyright 2022-2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-identifier: s32z270dc2_rtu1_r52@D
+identifier: s32z2xxdc2@D/s32z270/rtu1
 name: NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores (rev. D)
 type: mcu
 arch: arm

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig

@@ -1,9 +1,6 @@
-# Copyright 2022 NXP
+# Copyright 2022,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_BOARD_S32Z270DC2_RTU1_R52=y
-CONFIG_SOC_SERIES_S32ZE_R52=y
-CONFIG_SOC_S32Z27_R52=y
 CONFIG_XIP=n
 CONFIG_ISR_STACK_SIZE=512
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000

boards/nxp/s32z2xxdc2/support/debug.cmm

@@ -1,8 +1,8 @@
 ;*******************************************************************************
-;   Copyright 2022 NXP                                                         *
+;   Copyright 2022,2024 NXP                                                    *
 ;   SPDX-License-Identifier: Apache-2.0                                        *
 ;                                                                              *
-;   Lauterbach TRACE32 start-up script for debugging s32z270dc2_r52            *
+;   Lauterbach TRACE32 start-up script for debugging s32z2xxdc2                *
 ;                                                                              *
 ;*******************************************************************************
 

boards/nxp/s32z2xxdc2/support/flash.cmm

@@ -1,8 +1,8 @@
 ;*******************************************************************************
-;   Copyright 2022 NXP                                                         *
+;   Copyright 2022,2024 NXP                                                    *
 ;   SPDX-License-Identifier: Apache-2.0                                        *
 ;                                                                              *
-;   Lauterbach TRACE32 start-up script for flashing s32z270dc2_r52             *
+;   Lauterbach TRACE32 start-up script for flashing s32z2xxdc2                 *
 ;                                                                              *
 ;*******************************************************************************
 

samples/boards/nxp_s32/netc/README.rst

@@ -36,7 +36,7 @@ To build and run the sample application for use-case 1:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/boards/nxp_s32/netc
-   :board: s32z270dc2_rtu0_r52
+   :board: s32z2xxdc2/s32z270/rtu0
    :goals: build flash
 
 Once started, you should see the network interface details, for example:
@@ -59,7 +59,7 @@ To build and run the sample application for use-case 2:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/boards/nxp_s32/netc
-   :board: s32z270dc2_rtu0_r52
+   :board: s32z2xxdc2/s32z270/rtu0
    :goals: build flash
    :gen-args: -DDTC_OVERLAY_FILE="./vsi-and-psi.overlay"
 

samples/boards/nxp_s32/netc/sample.yaml

@@ -2,7 +2,9 @@ sample:
   description: Sample for show-casing the different use-cases of NXP S32 NETC driver
   name: NXP S32 NETC sample
 common:
-  platform_allow: s32z270dc2_rtu0_r52
+  platform_allow:
+    - s32z2xxdc2/s32z270/rtu0
+    - s32z2xxdc2@D/s32z270/rtu0
   depends_on: netif
   tags: net
 tests:

samples/drivers/watchdog/sample.yaml

@@ -18,10 +18,10 @@ tests:
   sample.drivers.watchdog:
     filter: not (CONFIG_SOC_FAMILY_STM32 or CONFIG_SOC_FAMILY_GD_GD32 or SOC_SERIES_GD32VF103)
     platform_exclude:
-      - s32z270dc2_rtu0_r52
+      - s32z2xxdc2/s32z270/rtu0
-      - s32z270dc2_rtu1_r52
+      - s32z2xxdc2/s32z270/rtu1
-      - s32z270dc2_rtu0_r52@D
+      - s32z2xxdc2@D/s32z270/rtu0
-      - s32z270dc2_rtu1_r52@D
+      - s32z2xxdc2@D/s32z270/rtu1
   sample.drivers.watchdog.stm32_wwdg:
     extra_args: DTC_OVERLAY_FILE=boards/stm32_wwdg.overlay
     filter: dt_compat_enabled("st,stm32-window-watchdog")
@@ -106,7 +106,7 @@ tests:
   sample.drivers.watchdog.s32z270dc2_r52:
     build_only: true
     platform_allow:
-      - s32z270dc2_rtu0_r52
+      - s32z2xxdc2/s32z270/rtu0
-      - s32z270dc2_rtu1_r52
+      - s32z2xxdc2/s32z270/rtu1
-      - s32z270dc2_rtu0_r52@D
+      - s32z2xxdc2@D/s32z270/rtu0
-      - s32z270dc2_rtu1_r52@D
+      - s32z2xxdc2@D/s32z270/rtu1

samples/subsys/task_wdt/sample.yaml

@@ -17,8 +17,10 @@ common:
       - "Task watchdog sample application."
   depends_on: watchdog
   platform_exclude:
-    - s32z270dc2_rtu0_r52
+    - s32z2xxdc2/s32z270/rtu0
-    - s32z270dc2_rtu1_r52
+    - s32z2xxdc2/s32z270/rtu1
+    - s32z2xxdc2@D/s32z270/rtu0
+    - s32z2xxdc2@D/s32z270/rtu1
 tests:
   sample.task_wdt:
     integration_platforms:

tests/drivers/gpio/gpio_hogs/testcase.yaml

@@ -12,8 +12,10 @@ tests:
       - nucleo_g474re
       - nrf52_bsim
       - mr_canhubk3
-      - s32z270dc2_rtu0_r52
+      - s32z2xxdc2/s32z270/rtu0
-      - s32z270dc2_rtu1_r52
+      - s32z2xxdc2/s32z270/rtu1
+      - s32z2xxdc2@D/s32z270/rtu0
+      - s32z2xxdc2@D/s32z270/rtu1
     integration_platforms:
       - native_sim
       - native_sim_64

tests/drivers/watchdog/wdt_basic_api/testcase.yaml

@@ -12,10 +12,10 @@ tests:
        CONFIG_SOC_FAMILY_GD_GD32 or SOC_SERIES_GD32VF103)
     platform_exclude:
       - mec15xxevb_assy6853
-      - s32z270dc2_rtu0_r52
+      - s32z2xxdc2/s32z270/rtu0
-      - s32z270dc2_rtu1_r52
+      - s32z2xxdc2/s32z270/rtu1
-      - s32z270dc2_rtu0_r52@D
+      - s32z2xxdc2@D/s32z270/rtu0
-      - s32z270dc2_rtu1_r52@D
+      - s32z2xxdc2@D/s32z270/rtu1
   drivers.watchdog.stm32wwdg:
     filter: dt_compat_enabled("st,stm32-window-watchdog") or dt_compat_enabled("st,stm32-watchdog")
     extra_args: DTC_OVERLAY_FILE="boards/stm32_wwdg.overlay"
@@ -117,10 +117,10 @@ tests:
   drivers.watchdog.nxp_s32:
     build_only: true
     platform_allow:
-      - s32z270dc2_rtu0_r52
+      - s32z2xxdc2/s32z270/rtu0
-      - s32z270dc2_rtu1_r52
+      - s32z2xxdc2/s32z270/rtu1
-      - s32z270dc2_rtu0_r52@D
+      - s32z2xxdc2@D/s32z270/rtu0
-      - s32z270dc2_rtu1_r52@D
+      - s32z2xxdc2@D/s32z270/rtu1
       - mr_canhubk3
   drivers.watchdog.mimxrt1050_evk_ti_tps382x:
     filter: dt_compat_enabled("ti,tps382x")

tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml

@@ -4,10 +4,10 @@
 tests:
   drivers.watchdog.reset_none:
     platform_allow:
-      - s32z270dc2_rtu0_r52
+      - s32z2xxdc2/s32z270/rtu0
-      - s32z270dc2_rtu1_r52
+      - s32z2xxdc2/s32z270/rtu1
-      - s32z270dc2_rtu0_r52@D
+      - s32z2xxdc2@D/s32z270/rtu0
-      - s32z270dc2_rtu1_r52@D
+      - s32z2xxdc2@D/s32z270/rtu1
     tags:
       - drivers
       - watchdog