Browse Source

boards: arm: nucleo_h745zi_q

add fdcan1, fdcan2 and usb_fs DT configurations

Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
pull/81485/head
Alexander Kozhinov 1 year ago committed by Anas Nashif
parent
commit
e68c7f2f73
  1. 2
      boards/st/nucleo_h745zi_q/doc/index.rst
  2. 11
      boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts
  3. 1
      boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml

2
boards/st/nucleo_h745zi_q/doc/index.rst

@ -112,6 +112,8 @@ features: @@ -112,6 +112,8 @@ features:
+-------------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-------------+------------+-------------------------------------+
| FDCAN | on-chip | CAN-FD Control Area Network |
+-------------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.

11
boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts

@ -144,3 +144,14 @@ zephyr_udc0: &usbotg_fs { @@ -144,3 +144,14 @@ zephyr_udc0: &usbotg_fs {
pinctrl-names = "default";
status = "okay";
};
&fdcan1 {
pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>;
/* HSE will be used by default. Uncomment below to enable APB1.2 120MHz clock */
/*
* clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
* <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
*/
pinctrl-names = "default";
status = "okay";
};

1
boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml

@ -16,6 +16,7 @@ supported: @@ -16,6 +16,7 @@ supported:
- counter
- i2c
- pwm
- can
- netif:eth
- spi
- usb_device

Loading…
Cancel
Save