Browse Source

arch: arm: Remove aarch32 directory

It doesn't make sense to keep the aarch32 directory in the
'arch/arm/core' directory as the aarch64 has been moved out.

This commit introduces the following major changes.

  1. Move all directories and files in 'arch/arm/core/aarch32' to
    'arch/arm/core' and remove the 'arch/arm/core/aarch32' directory.
  2. Move all directories and files in 'arch/include/aarch32' to
    'arch/include' and remove the 'arch/include/aarch32' directory.
  3. Remove the nested including in the 'arch/include/kernel_arch_func.h'
    and 'arch/include/offsets_short_arch.h' header files.
  4. Change the path string which is influenced by the changement 1
    and 2.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
pull/62165/head
Huifeng Zhang 2 years ago committed by Fabio Baltieri
parent
commit
df41deac1c
  1. 6
      CODEOWNERS
  2. 2
      arch/arm/CMakeLists.txt
  3. 4
      arch/arm/Kconfig
  4. 2
      arch/arm/core/CMakeLists.txt
  5. 0
      arch/arm/core/Kconfig
  6. 0
      arch/arm/core/Kconfig.vfp
  7. 0
      arch/arm/core/__aeabi_atexit.c
  8. 0
      arch/arm/core/cortex_a_r/CMakeLists.txt
  9. 0
      arch/arm/core/cortex_a_r/Kconfig
  10. 0
      arch/arm/core/cortex_a_r/__aeabi_read_tp.S
  11. 0
      arch/arm/core/cortex_a_r/cache.c
  12. 0
      arch/arm/core/cortex_a_r/exc.S
  13. 0
      arch/arm/core/cortex_a_r/exc_exit.S
  14. 0
      arch/arm/core/cortex_a_r/fault.c
  15. 0
      arch/arm/core/cortex_a_r/irq_init.c
  16. 0
      arch/arm/core/cortex_a_r/reboot.c
  17. 2
      arch/arm/core/cortex_a_r/reset.S
  18. 0
      arch/arm/core/cortex_a_r/semihost.c
  19. 2
      arch/arm/core/cortex_a_r/stacks.c
  20. 0
      arch/arm/core/cortex_a_r/tcm.c
  21. 0
      arch/arm/core/cortex_a_r/thread.c
  22. 0
      arch/arm/core/cortex_a_r/vector_table.S
  23. 0
      arch/arm/core/cortex_a_r/vector_table.h
  24. 0
      arch/arm/core/cortex_m/CMakeLists.txt
  25. 0
      arch/arm/core/cortex_m/Kconfig
  26. 0
      arch/arm/core/cortex_m/__aeabi_read_tp.S
  27. 0
      arch/arm/core/cortex_m/cache.c
  28. 0
      arch/arm/core/cortex_m/cmse/CMakeLists.txt
  29. 2
      arch/arm/core/cortex_m/cmse/arm_core_cmse.c
  30. 0
      arch/arm/core/cortex_m/coredump.c
  31. 2
      arch/arm/core/cortex_m/debug.c
  32. 0
      arch/arm/core/cortex_m/exc_exit.S
  33. 0
      arch/arm/core/cortex_m/fault.c
  34. 0
      arch/arm/core/cortex_m/fault_s.S
  35. 0
      arch/arm/core/cortex_m/fpu.c
  36. 0
      arch/arm/core/cortex_m/irq_init.c
  37. 0
      arch/arm/core/cortex_m/pm_s2ram.S
  38. 0
      arch/arm/core/cortex_m/pm_s2ram.c
  39. 0
      arch/arm/core/cortex_m/relay_vector_table.ld
  40. 0
      arch/arm/core/cortex_m/reset.S
  41. 0
      arch/arm/core/cortex_m/scb.c
  42. 0
      arch/arm/core/cortex_m/semihost.c
  43. 0
      arch/arm/core/cortex_m/thread.c
  44. 0
      arch/arm/core/cortex_m/thread_abort.c
  45. 2
      arch/arm/core/cortex_m/timing.c
  46. 0
      arch/arm/core/cortex_m/tz/CMakeLists.txt
  47. 0
      arch/arm/core/cortex_m/tz/Kconfig
  48. 4
      arch/arm/core/cortex_m/tz/arm_core_tz.c
  49. 0
      arch/arm/core/cortex_m/tz/secure_entry_functions.ld
  50. 0
      arch/arm/core/cortex_m/vector_table.S
  51. 0
      arch/arm/core/cortex_m/vector_table.h
  52. 0
      arch/arm/core/cortex_m/vector_table_pad.ld
  53. 0
      arch/arm/core/cortex_m/vt_pointer_section.ld
  54. 0
      arch/arm/core/cpu_idle.S
  55. 0
      arch/arm/core/fatal.c
  56. 0
      arch/arm/core/header.S
  57. 2
      arch/arm/core/irq_manage.c
  58. 0
      arch/arm/core/irq_offload.c
  59. 0
      arch/arm/core/irq_relay.S
  60. 0
      arch/arm/core/isr_wrapper.S
  61. 0
      arch/arm/core/mmu/CMakeLists.txt
  62. 0
      arch/arm/core/mmu/Kconfig
  63. 0
      arch/arm/core/mmu/arm_mmu.c
  64. 0
      arch/arm/core/mmu/arm_mmu_priv.h
  65. 0
      arch/arm/core/mpu/CMakeLists.txt
  66. 0
      arch/arm/core/mpu/Kconfig
  67. 0
      arch/arm/core/mpu/arm_core_mpu.c
  68. 0
      arch/arm/core/mpu/arm_core_mpu_dev.h
  69. 0
      arch/arm/core/mpu/arm_mpu.c
  70. 0
      arch/arm/core/mpu/arm_mpu_v7_internal.h
  71. 2
      arch/arm/core/mpu/arm_mpu_v8_internal.h
  72. 0
      arch/arm/core/mpu/cortex_a_r/arm_mpu_internal.h
  73. 0
      arch/arm/core/mpu/cortex_m/arm_mpu_internal.h
  74. 0
      arch/arm/core/mpu/nxp_mpu.c
  75. 0
      arch/arm/core/nmi.c
  76. 0
      arch/arm/core/nmi_on_reset.S
  77. 2
      arch/arm/core/prep_c.c
  78. 0
      arch/arm/core/swap.c
  79. 0
      arch/arm/core/swap_helper.S
  80. 0
      arch/arm/core/thread.c
  81. 0
      arch/arm/core/tls.c
  82. 0
      arch/arm/core/userspace.S
  83. 0
      arch/arm/core/vector_table.ld
  84. 0
      arch/arm/core/zimage_header.ld
  85. 93
      arch/arm/include/aarch32/kernel_arch_func.h
  86. 57
      arch/arm/include/aarch32/offsets_short_arch.h
  87. 0
      arch/arm/include/cortex_a_r/exc.h
  88. 0
      arch/arm/include/cortex_a_r/stack.h
  89. 0
      arch/arm/include/cortex_a_r/tcm.h
  90. 0
      arch/arm/include/cortex_m/cmse.h
  91. 0
      arch/arm/include/cortex_m/dwt.h
  92. 0
      arch/arm/include/cortex_m/exc.h
  93. 0
      arch/arm/include/cortex_m/stack.h
  94. 0
      arch/arm/include/cortex_m/tz.h
  95. 0
      arch/arm/include/cortex_m/tz_ns.h
  96. 8
      arch/arm/include/kernel_arch_data.h
  97. 82
      arch/arm/include/kernel_arch_func.h
  98. 47
      arch/arm/include/offsets_short_arch.h
  99. 4
      doc/hardware/arch/arm_cortex_m.rst
  100. 4
      doc/hardware/porting/arch.rst
  101. Some files were not shown because too many files have changed in this diff Show More

6
CODEOWNERS

@ -18,9 +18,9 @@
/MAINTAINERS.yml @MaureenHelm /MAINTAINERS.yml @MaureenHelm
/arch/arc/ @abrodkin @ruuddw @evgeniy-paltsev /arch/arc/ @abrodkin @ruuddw @evgeniy-paltsev
/arch/arm/ @MaureenHelm @galak @ioannisg /arch/arm/ @MaureenHelm @galak @ioannisg
/arch/arm/core/aarch32/cortex_m/cmse/ @ioannisg /arch/arm/core/cortex_m/cmse/ @ioannisg
/arch/arm/include/aarch32/cortex_m/cmse.h @ioannisg /arch/arm/include/cortex_m/cmse.h @ioannisg
/arch/arm/core/aarch32/cortex_a_r/ @MaureenHelm @galak @ioannisg @bbolen @stephanosio /arch/arm/core/cortex_a_r/ @MaureenHelm @galak @ioannisg @bbolen @stephanosio
/arch/arm64/ @carlocaione /arch/arm64/ @carlocaione
/arch/arm64/core/cortex_r/ @povergoing /arch/arm64/core/cortex_r/ @povergoing
/arch/arm64/core/xen/ @lorc @firscity /arch/arm64/core/xen/ @lorc @firscity

2
arch/arm/CMakeLists.txt

@ -2,4 +2,4 @@
set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-littlearm) set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-littlearm)
add_subdirectory(core/aarch32) add_subdirectory(core)

4
arch/arm/Kconfig

@ -69,7 +69,7 @@ config ARM_ON_EXIT_CPU_IDLE
observed on some SoCs caused by a memory access following WFI/WFE observed on some SoCs caused by a memory access following WFI/WFE
instructions. instructions.
rsource "core/aarch32/Kconfig" rsource "core/Kconfig"
rsource "core/aarch32/Kconfig.vfp" rsource "core/Kconfig.vfp"
endmenu endmenu

2
arch/arm/core/aarch32/CMakeLists.txt → arch/arm/core/CMakeLists.txt

@ -18,7 +18,7 @@ zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
zephyr_library_sources_ifdef(CONFIG_CPP __aeabi_atexit.c) zephyr_library_sources_ifdef(CONFIG_CPP __aeabi_atexit.c)
zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
zephyr_library_sources_ifdef(CONFIG_SW_VECTOR_RELAY irq_relay.S) zephyr_library_sources_ifdef(CONFIG_SW_VECTOR_RELAY irq_relay.S)
zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE ../common/tls.c) zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S) zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
zephyr_library_sources_ifdef(CONFIG_ARM_ZIMAGE_HEADER header.S) zephyr_library_sources_ifdef(CONFIG_ARM_ZIMAGE_HEADER header.S)

0
arch/arm/core/aarch32/Kconfig → arch/arm/core/Kconfig

0
arch/arm/core/aarch32/Kconfig.vfp → arch/arm/core/Kconfig.vfp

0
arch/arm/core/aarch32/__aeabi_atexit.c → arch/arm/core/__aeabi_atexit.c

0
arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt → arch/arm/core/cortex_a_r/CMakeLists.txt

0
arch/arm/core/aarch32/cortex_a_r/Kconfig → arch/arm/core/cortex_a_r/Kconfig

0
arch/arm/core/aarch32/cortex_a_r/__aeabi_read_tp.S → arch/arm/core/cortex_a_r/__aeabi_read_tp.S

0
arch/arm/core/aarch32/cortex_a_r/cache.c → arch/arm/core/cortex_a_r/cache.c

0
arch/arm/core/aarch32/cortex_a_r/exc.S → arch/arm/core/cortex_a_r/exc.S

0
arch/arm/core/aarch32/cortex_a_r/exc_exit.S → arch/arm/core/cortex_a_r/exc_exit.S

0
arch/arm/core/aarch32/cortex_a_r/fault.c → arch/arm/core/cortex_a_r/fault.c

0
arch/arm/core/aarch32/cortex_a_r/irq_init.c → arch/arm/core/cortex_a_r/irq_init.c

0
arch/arm/core/aarch32/cortex_a_r/reboot.c → arch/arm/core/cortex_a_r/reboot.c

2
arch/arm/core/aarch32/cortex_a_r/reset.S → arch/arm/core/cortex_a_r/reset.S

@ -16,7 +16,7 @@
#include <zephyr/linker/sections.h> #include <zephyr/linker/sections.h>
#include <zephyr/arch/cpu.h> #include <zephyr/arch/cpu.h>
#include <offsets_short.h> #include <offsets_short.h>
#include <aarch32/cortex_a_r/tcm.h> #include <cortex_a_r/tcm.h>
#include "vector_table.h" #include "vector_table.h"
_ASM_FILE_PROLOGUE _ASM_FILE_PROLOGUE

0
arch/arm/core/aarch32/cortex_a_r/semihost.c → arch/arm/core/cortex_a_r/semihost.c

2
arch/arm/core/aarch32/cortex_a_r/stacks.c → arch/arm/core/cortex_a_r/stacks.c

@ -5,7 +5,7 @@
*/ */
#include <zephyr/kernel.h> #include <zephyr/kernel.h>
#include <aarch32/cortex_a_r/stack.h> #include <cortex_a_r/stack.h>
#include <string.h> #include <string.h>
#include <kernel_internal.h> #include <kernel_internal.h>

0
arch/arm/core/aarch32/cortex_a_r/tcm.c → arch/arm/core/cortex_a_r/tcm.c

0
arch/arm/core/aarch32/cortex_a_r/thread.c → arch/arm/core/cortex_a_r/thread.c

0
arch/arm/core/aarch32/cortex_a_r/vector_table.S → arch/arm/core/cortex_a_r/vector_table.S

0
arch/arm/core/aarch32/cortex_a_r/vector_table.h → arch/arm/core/cortex_a_r/vector_table.h

0
arch/arm/core/aarch32/cortex_m/CMakeLists.txt → arch/arm/core/cortex_m/CMakeLists.txt

0
arch/arm/core/aarch32/cortex_m/Kconfig → arch/arm/core/cortex_m/Kconfig

0
arch/arm/core/aarch32/cortex_m/__aeabi_read_tp.S → arch/arm/core/cortex_m/__aeabi_read_tp.S

0
arch/arm/core/aarch32/cortex_m/cache.c → arch/arm/core/cortex_m/cache.c

0
arch/arm/core/aarch32/cortex_m/cmse/CMakeLists.txt → arch/arm/core/cortex_m/cmse/CMakeLists.txt

2
arch/arm/core/aarch32/cortex_m/cmse/arm_core_cmse.c → arch/arm/core/cortex_m/cmse/arm_core_cmse.c

@ -5,7 +5,7 @@
*/ */
#include <zephyr/kernel.h> #include <zephyr/kernel.h>
#include <aarch32/cortex_m/cmse.h> #include <cortex_m/cmse.h>
int arm_cmse_mpu_region_get(uint32_t addr) int arm_cmse_mpu_region_get(uint32_t addr)
{ {

0
arch/arm/core/aarch32/cortex_m/coredump.c → arch/arm/core/cortex_m/coredump.c

2
arch/arm/core/aarch32/cortex_m/debug.c → arch/arm/core/cortex_m/debug.c

@ -12,7 +12,7 @@
#include <zephyr/kernel.h> #include <zephyr/kernel.h>
#include <zephyr/device.h> #include <zephyr/device.h>
#include <aarch32/cortex_m/dwt.h> #include <cortex_m/dwt.h>
/** /**
* @brief Assess whether a debug monitor event should be treated as an error * @brief Assess whether a debug monitor event should be treated as an error

0
arch/arm/core/aarch32/cortex_m/exc_exit.S → arch/arm/core/cortex_m/exc_exit.S

0
arch/arm/core/aarch32/cortex_m/fault.c → arch/arm/core/cortex_m/fault.c

0
arch/arm/core/aarch32/cortex_m/fault_s.S → arch/arm/core/cortex_m/fault_s.S

0
arch/arm/core/aarch32/cortex_m/fpu.c → arch/arm/core/cortex_m/fpu.c

0
arch/arm/core/aarch32/cortex_m/irq_init.c → arch/arm/core/cortex_m/irq_init.c

0
arch/arm/core/aarch32/cortex_m/pm_s2ram.S → arch/arm/core/cortex_m/pm_s2ram.S

0
arch/arm/core/aarch32/cortex_m/pm_s2ram.c → arch/arm/core/cortex_m/pm_s2ram.c

0
arch/arm/core/aarch32/cortex_m/relay_vector_table.ld → arch/arm/core/cortex_m/relay_vector_table.ld

0
arch/arm/core/aarch32/cortex_m/reset.S → arch/arm/core/cortex_m/reset.S

0
arch/arm/core/aarch32/cortex_m/scb.c → arch/arm/core/cortex_m/scb.c

0
arch/arm/core/aarch32/cortex_m/semihost.c → arch/arm/core/cortex_m/semihost.c

0
arch/arm/core/aarch32/cortex_m/thread.c → arch/arm/core/cortex_m/thread.c

0
arch/arm/core/aarch32/cortex_m/thread_abort.c → arch/arm/core/cortex_m/thread_abort.c

2
arch/arm/core/aarch32/cortex_m/timing.c → arch/arm/core/cortex_m/timing.c

@ -14,7 +14,7 @@
#include <zephyr/init.h> #include <zephyr/init.h>
#include <zephyr/kernel.h> #include <zephyr/kernel.h>
#include <zephyr/timing/timing.h> #include <zephyr/timing/timing.h>
#include <aarch32/cortex_m/dwt.h> #include <cortex_m/dwt.h>
#include <cmsis_core.h> #include <cmsis_core.h>
#include <zephyr/sys_clock.h> #include <zephyr/sys_clock.h>

0
arch/arm/core/aarch32/cortex_m/tz/CMakeLists.txt → arch/arm/core/cortex_m/tz/CMakeLists.txt

0
arch/arm/core/aarch32/cortex_m/tz/Kconfig → arch/arm/core/cortex_m/tz/Kconfig

4
arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c → arch/arm/core/cortex_m/tz/arm_core_tz.c

@ -5,8 +5,8 @@
*/ */
#include <cmsis_core.h> #include <cmsis_core.h>
#include <aarch32/cortex_m/tz.h> #include <cortex_m/tz.h>
#include <aarch32/cortex_m/exc.h> #include <cortex_m/exc.h>
static void configure_nonsecure_vtor_offset(uint32_t vtor_ns) static void configure_nonsecure_vtor_offset(uint32_t vtor_ns)
{ {

0
arch/arm/core/aarch32/cortex_m/tz/secure_entry_functions.ld → arch/arm/core/cortex_m/tz/secure_entry_functions.ld

0
arch/arm/core/aarch32/cortex_m/vector_table.S → arch/arm/core/cortex_m/vector_table.S

0
arch/arm/core/aarch32/cortex_m/vector_table.h → arch/arm/core/cortex_m/vector_table.h

0
arch/arm/core/aarch32/cortex_m/vector_table_pad.ld → arch/arm/core/cortex_m/vector_table_pad.ld

0
arch/arm/core/aarch32/cortex_m/vt_pointer_section.ld → arch/arm/core/cortex_m/vt_pointer_section.ld

0
arch/arm/core/aarch32/cpu_idle.S → arch/arm/core/cpu_idle.S

0
arch/arm/core/aarch32/fatal.c → arch/arm/core/fatal.c

0
arch/arm/core/aarch32/header.S → arch/arm/core/header.S

2
arch/arm/core/aarch32/irq_manage.c → arch/arm/core/irq_manage.c

@ -174,7 +174,7 @@ void _arch_isr_direct_pm(void)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
/* Lock all interrupts. irq_lock() will on this CPU only disable those /* Lock all interrupts. irq_lock() will on this CPU only disable those
* lower than BASEPRI, which is not what we want. See comments in * lower than BASEPRI, which is not what we want. See comments in
* arch/arm/core/aarch32/isr_wrapper.S * arch/arm/core/isr_wrapper.S
*/ */
__asm__ volatile("cpsid i" : : : "memory"); __asm__ volatile("cpsid i" : : : "memory");
#else #else

0
arch/arm/core/aarch32/irq_offload.c → arch/arm/core/irq_offload.c

0
arch/arm/core/aarch32/irq_relay.S → arch/arm/core/irq_relay.S

0
arch/arm/core/aarch32/isr_wrapper.S → arch/arm/core/isr_wrapper.S

0
arch/arm/core/aarch32/mmu/CMakeLists.txt → arch/arm/core/mmu/CMakeLists.txt

0
arch/arm/core/aarch32/mmu/Kconfig → arch/arm/core/mmu/Kconfig

0
arch/arm/core/aarch32/mmu/arm_mmu.c → arch/arm/core/mmu/arm_mmu.c

0
arch/arm/core/aarch32/mmu/arm_mmu_priv.h → arch/arm/core/mmu/arm_mmu_priv.h

0
arch/arm/core/aarch32/mpu/CMakeLists.txt → arch/arm/core/mpu/CMakeLists.txt

0
arch/arm/core/aarch32/mpu/Kconfig → arch/arm/core/mpu/Kconfig

0
arch/arm/core/aarch32/mpu/arm_core_mpu.c → arch/arm/core/mpu/arm_core_mpu.c

0
arch/arm/core/aarch32/mpu/arm_core_mpu_dev.h → arch/arm/core/mpu/arm_core_mpu_dev.h

0
arch/arm/core/aarch32/mpu/arm_mpu.c → arch/arm/core/mpu/arm_mpu.c

0
arch/arm/core/aarch32/mpu/arm_mpu_v7_internal.h → arch/arm/core/mpu/arm_mpu_v7_internal.h

2
arch/arm/core/aarch32/mpu/arm_mpu_v8_internal.h → arch/arm/core/mpu/arm_mpu_v8_internal.h

@ -8,7 +8,7 @@
#ifndef ZEPHYR_ARCH_ARM_CORE_AARCH32_MPU_ARM_MPU_V8_INTERNAL_H_ #ifndef ZEPHYR_ARCH_ARM_CORE_AARCH32_MPU_ARM_MPU_V8_INTERNAL_H_
#define ZEPHYR_ARCH_ARM_CORE_AARCH32_MPU_ARM_MPU_V8_INTERNAL_H_ #define ZEPHYR_ARCH_ARM_CORE_AARCH32_MPU_ARM_MPU_V8_INTERNAL_H_
#include <aarch32/cortex_m/cmse.h> #include <cortex_m/cmse.h>
#define LOG_LEVEL CONFIG_MPU_LOG_LEVEL #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
#include <zephyr/sys/math_extras.h> #include <zephyr/sys/math_extras.h>

0
arch/arm/core/aarch32/mpu/cortex_a_r/arm_mpu_internal.h → arch/arm/core/mpu/cortex_a_r/arm_mpu_internal.h

0
arch/arm/core/aarch32/mpu/cortex_m/arm_mpu_internal.h → arch/arm/core/mpu/cortex_m/arm_mpu_internal.h

0
arch/arm/core/aarch32/mpu/nxp_mpu.c → arch/arm/core/mpu/nxp_mpu.c

0
arch/arm/core/aarch32/nmi.c → arch/arm/core/nmi.c

0
arch/arm/core/aarch32/nmi_on_reset.S → arch/arm/core/nmi_on_reset.S

2
arch/arm/core/aarch32/prep_c.c → arch/arm/core/prep_c.c

@ -26,7 +26,7 @@
#endif #endif
#if defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) #if defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
#include <aarch32/cortex_a_r/stack.h> #include <cortex_a_r/stack.h>
#endif #endif
#if defined(__GNUC__) #if defined(__GNUC__)

0
arch/arm/core/aarch32/swap.c → arch/arm/core/swap.c

0
arch/arm/core/aarch32/swap_helper.S → arch/arm/core/swap_helper.S

0
arch/arm/core/aarch32/thread.c → arch/arm/core/thread.c

0
arch/arm/core/common/tls.c → arch/arm/core/tls.c

0
arch/arm/core/aarch32/userspace.S → arch/arm/core/userspace.S

0
arch/arm/core/aarch32/vector_table.ld → arch/arm/core/vector_table.ld

0
arch/arm/core/aarch32/zimage_header.ld → arch/arm/core/zimage_header.ld

93
arch/arm/include/aarch32/kernel_arch_func.h

@ -1,93 +0,0 @@
/*
* Copyright (c) 2013-2016 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Private kernel definitions (ARM)
*
* This file contains private kernel function definitions and various
* other definitions for the 32-bit ARM Cortex-A/R/M processor architecture
* family.
*
* This file is also included by assembly language files which must #define
* _ASMLANGUAGE before including this header file. Note that kernel
* assembly source files obtains structure offset values via "absolute symbols"
* in the offsets.o module.
*/
#ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_KERNEL_ARCH_FUNC_H_
#define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_KERNEL_ARCH_FUNC_H_
#include <kernel_arch_data.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
extern void z_arm_fault_init(void);
extern void z_arm_cpu_idle_init(void);
#ifdef CONFIG_ARM_MPU
extern void z_arm_configure_static_mpu_regions(void);
extern void z_arm_configure_dynamic_mpu_regions(struct k_thread *thread);
extern int z_arm_mpu_init(void);
#endif /* CONFIG_ARM_MPU */
#ifdef CONFIG_ARM_AARCH32_MMU
extern int z_arm_mmu_init(void);
#endif /* CONFIG_ARM_AARCH32_MMU */
static ALWAYS_INLINE void arch_kernel_init(void)
{
z_arm_interrupt_stack_setup();
z_arm_exc_setup();
z_arm_fault_init();
z_arm_cpu_idle_init();
z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
z_arm_mpu_init();
/* Configure static memory map. This will program MPU regions,
* to set up access permissions for fixed memory sections, such
* as Application Memory or No-Cacheable SRAM area.
*
* This function is invoked once, upon system initialization.
*/
z_arm_configure_static_mpu_regions();
#endif /* CONFIG_ARM_MPU */
#if defined(CONFIG_ARM_AARCH32_MMU)
z_arm_mmu_init();
#endif /* CONFIG_ARM_AARCH32_MMU */
}
static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
thread->arch.swap_return_value = value;
}
#if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_CPU_CORTEX_M)
extern FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(
k_thread_entry_t main_func,
void *p1, void *p2, void *p3);
#define ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING \
z_arm_switch_to_main_no_multithreading
#endif /* !CONFIG_MULTITHREADING && CONFIG_CPU_CORTEX_M */
extern FUNC_NORETURN void z_arm_userspace_enter(k_thread_entry_t user_entry,
void *p1, void *p2, void *p3,
uint32_t stack_end,
uint32_t stack_start);
extern void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_KERNEL_ARCH_FUNC_H_ */

57
arch/arm/include/aarch32/offsets_short_arch.h

@ -1,57 +0,0 @@
/*
* Copyright (c) 2016 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_OFFSETS_SHORT_ARCH_H_
#define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_OFFSETS_SHORT_ARCH_H_
#include <offsets.h>
/* kernel */
/* nothing for now */
/* end - kernel */
/* threads */
#define _thread_offset_to_basepri \
(___thread_t_arch_OFFSET + ___thread_arch_t_basepri_OFFSET)
#define _thread_offset_to_preempt_float \
(___thread_t_arch_OFFSET + ___thread_arch_t_preempt_float_OFFSET)
#if defined(CONFIG_USERSPACE) || defined(CONFIG_FPU_SHARING)
#define _thread_offset_to_mode \
(___thread_t_arch_OFFSET + ___thread_arch_t_mode_OFFSET)
#endif
#if defined(CONFIG_ARM_STORE_EXC_RETURN)
#define _thread_offset_to_mode_exc_return \
(___thread_t_arch_OFFSET + ___thread_arch_t_mode_exc_return_OFFSET)
#endif
#ifdef CONFIG_USERSPACE
#define _thread_offset_to_priv_stack_start \
(___thread_t_arch_OFFSET + ___thread_arch_t_priv_stack_start_OFFSET)
#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
#define _thread_offset_to_priv_stack_end \
(___thread_t_arch_OFFSET + ___thread_arch_t_priv_stack_end_OFFSET)
#define _thread_offset_to_sp_usr \
(___thread_t_arch_OFFSET + ___thread_arch_t_sp_usr_OFFSET)
#endif
#endif
#if defined(CONFIG_THREAD_STACK_INFO)
#define _thread_offset_to_stack_info_start \
(___thread_stack_info_t_start_OFFSET + ___thread_t_stack_info_OFFSET)
#endif
/* end - threads */
#endif /* ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_OFFSETS_SHORT_ARCH_H_ */

0
arch/arm/include/aarch32/cortex_a_r/exc.h → arch/arm/include/cortex_a_r/exc.h

0
arch/arm/include/aarch32/cortex_a_r/stack.h → arch/arm/include/cortex_a_r/stack.h

0
arch/arm/include/aarch32/cortex_a_r/tcm.h → arch/arm/include/cortex_a_r/tcm.h

0
arch/arm/include/aarch32/cortex_m/cmse.h → arch/arm/include/cortex_m/cmse.h

0
arch/arm/include/aarch32/cortex_m/dwt.h → arch/arm/include/cortex_m/dwt.h

0
arch/arm/include/aarch32/cortex_m/exc.h → arch/arm/include/cortex_m/exc.h

0
arch/arm/include/aarch32/cortex_m/stack.h → arch/arm/include/cortex_m/stack.h

0
arch/arm/include/aarch32/cortex_m/tz.h → arch/arm/include/cortex_m/tz.h

0
arch/arm/include/aarch32/cortex_m/tz_ns.h → arch/arm/include/cortex_m/tz_ns.h

8
arch/arm/include/kernel_arch_data.h

@ -25,11 +25,11 @@
#include <zephyr/arch/cpu.h> #include <zephyr/arch/cpu.h>
#if defined(CONFIG_CPU_CORTEX_M) #if defined(CONFIG_CPU_CORTEX_M)
#include <aarch32/cortex_m/stack.h> #include <cortex_m/stack.h>
#include <aarch32/cortex_m/exc.h> #include <cortex_m/exc.h>
#elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) #elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
#include <aarch32/cortex_a_r/stack.h> #include <cortex_a_r/stack.h>
#include <aarch32/cortex_a_r/exc.h> #include <cortex_a_r/exc.h>
#endif #endif
#ifndef _ASMLANGUAGE #ifndef _ASMLANGUAGE

82
arch/arm/include/kernel_arch_func.h

@ -3,10 +3,90 @@
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
/**
* @file
* @brief Private kernel definitions (ARM)
*
* This file contains private kernel function definitions and various
* other definitions for the 32-bit ARM Cortex-A/R/M processor architecture
* family.
*
* This file is also included by assembly language files which must #define
* _ASMLANGUAGE before including this header file. Note that kernel
* assembly source files obtains structure offset values via "absolute symbols"
* in the offsets.o module.
*/
#ifndef ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_ #ifndef ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_
#define ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_ #define ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_
#include <aarch32/kernel_arch_func.h> #include <kernel_arch_data.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
extern void z_arm_fault_init(void);
extern void z_arm_cpu_idle_init(void);
#ifdef CONFIG_ARM_MPU
extern void z_arm_configure_static_mpu_regions(void);
extern void z_arm_configure_dynamic_mpu_regions(struct k_thread *thread);
extern int z_arm_mpu_init(void);
#endif /* CONFIG_ARM_MPU */
#ifdef CONFIG_ARM_AARCH32_MMU
extern int z_arm_mmu_init(void);
#endif /* CONFIG_ARM_AARCH32_MMU */
static ALWAYS_INLINE void arch_kernel_init(void)
{
z_arm_interrupt_stack_setup();
z_arm_exc_setup();
z_arm_fault_init();
z_arm_cpu_idle_init();
z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
z_arm_mpu_init();
/* Configure static memory map. This will program MPU regions,
* to set up access permissions for fixed memory sections, such
* as Application Memory or No-Cacheable SRAM area.
*
* This function is invoked once, upon system initialization.
*/
z_arm_configure_static_mpu_regions();
#endif /* CONFIG_ARM_MPU */
#if defined(CONFIG_ARM_AARCH32_MMU)
z_arm_mmu_init();
#endif /* CONFIG_ARM_AARCH32_MMU */
}
static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
thread->arch.swap_return_value = value;
}
#if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_CPU_CORTEX_M)
extern FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(
k_thread_entry_t main_func,
void *p1, void *p2, void *p3);
#define ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING \
z_arm_switch_to_main_no_multithreading
#endif /* !CONFIG_MULTITHREADING && CONFIG_CPU_CORTEX_M */
extern FUNC_NORETURN void z_arm_userspace_enter(k_thread_entry_t user_entry,
void *p1, void *p2, void *p3,
uint32_t stack_end,
uint32_t stack_start);
extern void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_ */ #endif /* ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_ */

47
arch/arm/include/offsets_short_arch.h

@ -7,6 +7,51 @@
#ifndef ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_ #ifndef ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_
#define ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_ #define ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_
#include <aarch32/offsets_short_arch.h> #include <offsets.h>
/* kernel */
/* nothing for now */
/* end - kernel */
/* threads */
#define _thread_offset_to_basepri \
(___thread_t_arch_OFFSET + ___thread_arch_t_basepri_OFFSET)
#define _thread_offset_to_preempt_float \
(___thread_t_arch_OFFSET + ___thread_arch_t_preempt_float_OFFSET)
#if defined(CONFIG_USERSPACE) || defined(CONFIG_FPU_SHARING)
#define _thread_offset_to_mode \
(___thread_t_arch_OFFSET + ___thread_arch_t_mode_OFFSET)
#endif
#if defined(CONFIG_ARM_STORE_EXC_RETURN)
#define _thread_offset_to_mode_exc_return \
(___thread_t_arch_OFFSET + ___thread_arch_t_mode_exc_return_OFFSET)
#endif
#ifdef CONFIG_USERSPACE
#define _thread_offset_to_priv_stack_start \
(___thread_t_arch_OFFSET + ___thread_arch_t_priv_stack_start_OFFSET)
#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
#define _thread_offset_to_priv_stack_end \
(___thread_t_arch_OFFSET + ___thread_arch_t_priv_stack_end_OFFSET)
#define _thread_offset_to_sp_usr \
(___thread_t_arch_OFFSET + ___thread_arch_t_sp_usr_OFFSET)
#endif
#endif
#if defined(CONFIG_THREAD_STACK_INFO)
#define _thread_offset_to_stack_info_start \
(___thread_stack_info_t_start_OFFSET + ___thread_t_stack_info_OFFSET)
#endif
/* end - threads */
#endif /* ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_ */ #endif /* ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_ */

4
doc/hardware/arch/arm_cortex_m.rst

@ -169,7 +169,7 @@ PendSV exception return sequence restores the new thread's caller-saved register
return address, as part of unstacking the exception stack frame. return address, as part of unstacking the exception stack frame.
The implementation of the context-switch mechanism is present in The implementation of the context-switch mechanism is present in
:file:`arch/arm/core/aarch32/swap_helper.S`. :file:`arch/arm/core/swap_helper.S`.
Stack limit checking (Arm v8-M) Stack limit checking (Arm v8-M)
------------------------------- -------------------------------
@ -337,7 +337,7 @@ CPU Idling
The Cortex-M architecture port implements both k_cpu_idle() The Cortex-M architecture port implements both k_cpu_idle()
and k_cpu_atomic_idle(). The implementation is present in and k_cpu_atomic_idle(). The implementation is present in
:file:`arch/arm/core/aarch32/cpu_idle.S`. :file:`arch/arm/core/cpu_idle.S`.
In both implementations, the processor In both implementations, the processor
will attempt to put the core to low power mode. will attempt to put the core to low power mode.

4
doc/hardware/porting/arch.rst

@ -160,7 +160,7 @@ we strongly suggest that handlers at least print some debug information. The
information helps figuring out what went wrong when hitting an exception that information helps figuring out what went wrong when hitting an exception that
is a fault, like divide-by-zero or invalid memory access, or an interrupt that is a fault, like divide-by-zero or invalid memory access, or an interrupt that
is not expected (:dfn:`spurious interrupt`). See the ARM implementation in is not expected (:dfn:`spurious interrupt`). See the ARM implementation in
:zephyr_file:`arch/arm/core/aarch32/cortex_m/fault.c` for an example. :zephyr_file:`arch/arm/core/cortex_m/fault.c` for an example.
Thread Context Switching Thread Context Switching
************************ ************************
@ -299,7 +299,7 @@ gracefully exits its entry point function.
This means implementing an architecture-specific version of This means implementing an architecture-specific version of
:c:func:`k_thread_abort`, and setting the Kconfig option :c:func:`k_thread_abort`, and setting the Kconfig option
:kconfig:option:`CONFIG_ARCH_HAS_THREAD_ABORT` as needed for the architecture (e.g. see :kconfig:option:`CONFIG_ARCH_HAS_THREAD_ABORT` as needed for the architecture (e.g. see
:zephyr_file:`arch/arm/core/aarch32/cortex_m/Kconfig`). :zephyr_file:`arch/arm/core/cortex_m/Kconfig`).
Thread Local Storage Thread Local Storage
******************** ********************

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