Browse Source
Remove qemu_nios2, more removals will follow. Part of #89280 Signed-off-by: Anas Nashif <anas.nashif@intel.com>pull/86868/merge
Anas Nashif
2 months ago
25 changed files with 2 additions and 700 deletions
@ -1,5 +0,0 @@ |
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# Copyright (c) 2018 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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config BOARD_QEMU_NIOS2 |
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select QEMU_TARGET |
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@ -1,9 +0,0 @@ |
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# Copyright (c) 2018 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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if BOARD_QEMU_NIOS2 |
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config BUILD_OUTPUT_BIN |
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default n |
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endif |
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@ -1,5 +0,0 @@ |
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# Copyright (c) 2018 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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config BOARD_QEMU_NIOS2 |
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select SOC_QEMU_NIOS2 |
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@ -1,13 +0,0 @@ |
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# Copyright (c) 2018 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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set(SUPPORTED_EMU_PLATFORMS qemu) |
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set(QEMU_CPU_TYPE_${ARCH} nios2) |
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set(QEMU_FLAGS_${ARCH} |
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-machine altera_10m50_zephyr |
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-nographic |
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) |
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board_set_debugger_ifnset(qemu) |
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@ -1,6 +0,0 @@ |
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board: |
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name: qemu_nios2 |
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full_name: QEMU Emulation for Altera Nios-II |
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vendor: altr |
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socs: |
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- name: qemu_nios2 |
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@ -1,127 +0,0 @@ |
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.. zephyr:board:: qemu_nios2 |
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Overview |
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******** |
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This board configuration will use QEMU to emulate the Altera MAX 10 platform. |
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This configuration provides support for an Altera Nios-II CPU and these devices: |
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* Internal Interrupt Controller |
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* Altera Avalon Timer |
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* NS16550 UART |
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.. note:: |
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This board configuration makes no claims about its suitability for use |
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with an actual ti_lm3s6965 hardware system, or any other hardware system. |
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Hardware |
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******** |
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Supported Features |
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================== |
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The following hardware features are supported: |
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+--------------+------------+----------------------+ |
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| Interface | Controller | Driver/Component | |
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+==============+============+======================+ |
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| IIC | on-chip | Internal interrupt | |
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| | | controller | |
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+--------------+------------+----------------------+ |
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| NS16550 | on-chip | serial port | |
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| UART | | | |
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+--------------+------------+----------------------+ |
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| TIMER | on-chip | system clock | |
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+--------------+------------+----------------------+ |
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The kernel currently does not support other hardware features on this platform. |
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Devices |
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======== |
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System Clock |
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------------ |
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This board configuration uses a system clock frequency of 50 MHz. |
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Serial Port |
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----------- |
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This board configuration uses a single serial communication channel with the |
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CPU's UART0. |
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If SLIP networking is enabled (see below), an additional serial port will be |
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used for it. |
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Known Problems or Limitations |
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============================== |
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The following platform features are unsupported: |
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* Memory protection through optional MPU. However, using a XIP kernel |
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effectively provides TEXT/RODATA write protection in ROM. |
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* Writing to the hardware's flash memory |
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* Serial port in Direct Memory Access (DMA) mode |
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* Serial Peripheral Interface (SPI) flash |
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* General-Purpose Input/Output (GPIO) |
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* Inter-Integrated Circuit (I2C) |
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* Ethernet |
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Programming and Debugging |
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************************* |
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.. zephyr:board-supported-runners:: |
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Use this configuration to run basic Zephyr applications and kernel tests in the QEMU |
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emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample: |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/synchronization |
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:host-os: unix |
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:board: qemu_nios2 |
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:goals: run |
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This will build an image with the synchronization sample app, boot it using |
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QEMU, and display the following console output: |
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.. code-block:: console |
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***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 ***** |
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threadA: Hello World from arm! |
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threadB: Hello World from arm! |
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threadA: Hello World from arm! |
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threadB: Hello World from arm! |
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threadA: Hello World from arm! |
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threadB: Hello World from arm! |
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threadA: Hello World from arm! |
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threadB: Hello World from arm! |
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threadA: Hello World from arm! |
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threadB: Hello World from arm! |
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Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. |
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Debugging |
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========= |
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Refer to the detailed overview about :ref:`application_debugging`. |
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Networking |
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========== |
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The board supports SLIP networking over an emulated serial port |
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(``CONFIG_NET_SLIP_TAP=y``). The detailed setup is described in |
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:ref:`networking_with_qemu`. |
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References |
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********** |
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* `CPU Documentation <https://www.altera.com/en_US/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf>`_ |
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* `Nios II Processor Booting Methods in MAX 10 FPGA Devices <https://www.altera.com/en_US/pdfs/literature/an/an730.pdf>`_ |
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* `Embedded Peripherals IP User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf>`_ |
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* `MAX 10 FPGA Configuration User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_config.pdf>`_ |
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* `MAX 10 FPGA Development Kit User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug-max10m50-fpga-dev-kit.pdf>`_ |
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* `Nios II Command-Line Tools <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/edh_ed51004.pdf>`_ |
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* `Quartus II Scripting Reference Manual <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/tclscriptrefmnl.pdf>`_ |
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.. _Altera Lite Distribution: http://dl.altera.com/?edition=lite |
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@ -1,32 +0,0 @@ |
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/* SPDX-License-Identifier: Apache-2.0 */ |
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/dts-v1/; |
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#include <intel/nios2-qemu.dtsi> |
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/ { |
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model = "qemu_nios2"; |
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compatible = "qemu,nios2"; |
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aliases { |
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uart-0 = &jtag_uart; |
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uart-1 = &ns16550_uart; |
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}; |
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chosen { |
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zephyr,sram = &sram0; |
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zephyr,flash = &flash0; |
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zephyr,console = &ns16550_uart; |
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zephyr,shell-uart = &ns16550_uart; |
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}; |
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}; |
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&jtag_uart { |
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status = "okay"; |
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current-speed = <115200>; |
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}; |
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&ns16550_uart { |
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status = "okay"; |
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current-speed = <115200>; |
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}; |
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@ -1,16 +0,0 @@ |
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identifier: qemu_nios2 |
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name: QEMU Emulation for NIOS II |
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type: qemu |
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simulation: |
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- name: qemu |
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arch: nios2 |
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ram: 128 |
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flash: 128 |
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toolchain: |
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- zephyr |
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testing: |
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default: true |
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ignore_tags: |
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- net |
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- bluetooth |
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vendor: qemu |
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@ -1,10 +0,0 @@ |
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# Copyright (c) 2018 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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CONFIG_HAS_ALTERA_HAL=y |
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CONFIG_CONSOLE=y |
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CONFIG_SERIAL=y |
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CONFIG_UART_CONSOLE=y |
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CONFIG_INCLUDE_RESET_VECTOR=n |
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CONFIG_EXTRA_EXCEPTION_INFO=y |
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CONFIG_QEMU_ICOUNT_SHIFT=4 |
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@ -1,7 +0,0 @@ |
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# Copyright (c) 2018 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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zephyr_include_directories(include) |
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zephyr_include_directories(.) |
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") |
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@ -1,8 +0,0 @@ |
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# Copyright (c) 2018 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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config SOC_QEMU_NIOS2 |
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select NIOS2 |
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select HAS_MUL_INSTRUCTION |
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select HAS_DIV_INSTRUCTION |
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select HAS_MULX_INSTRUCTION |
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@ -1,9 +0,0 @@ |
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# Copyright (c) 2018 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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if SOC_QEMU_NIOS2 |
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config SYS_CLOCK_HW_CYCLES_PER_SEC |
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default 50000000 |
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endif |
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@ -1,8 +0,0 @@ |
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# Copyright (c) 2018 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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config SOC_QEMU_NIOS2 |
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bool |
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config SOC |
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default "qemu_nios2" if SOC_QEMU_NIOS2 |
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@ -1,14 +0,0 @@ |
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/*
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* Copyright (c) 2016 Intel Corporation |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <system.h> |
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/* To simulate XIP on QEMU, we split RAM into two chunks, with the
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* higher-addressed chunk considered "ROM" |
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*/ |
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#define _RESET_VECTOR _ROM_ADDR |
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#define _EXC_VECTOR ALT_CPU_EXCEPTION_ADDR |
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/*
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* linker.h - Linker script mapping information |
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* |
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* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da' |
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* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo |
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* |
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* Generated: Tue May 03 11:35:27 MYT 2016 |
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*/ |
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/*
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* DO NOT MODIFY THIS FILE |
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* |
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* Changing this file will have subtle consequences |
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* which will almost certainly lead to a nonfunctioning |
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* system. If you do modify this file, be aware that your |
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* changes will be overwritten and lost when this file |
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* is generated again. |
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* |
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* DO NOT MODIFY THIS FILE |
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*/ |
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/*
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* License Agreement |
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* |
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* Copyright (c) 2008 |
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* Altera Corporation, San Jose, California, USA. |
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* All rights reserved. |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a |
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* copy of this software and associated documentation files (the "Software"), |
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* to deal in the Software without restriction, including without limitation |
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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* and/or sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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* DEALINGS IN THE SOFTWARE. |
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* |
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* This agreement shall be governed in all respects by the laws of the State |
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* of California and by the laws of the United States of America. |
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*/ |
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#ifndef __LINKER_H_ |
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#define __LINKER_H_ |
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/*
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* BSP controls alt_load() behavior in crt0. |
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* |
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*/ |
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#define ALT_LOAD_EXPLICITLY_CONTROLLED |
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/*
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* Base address and span (size in bytes) of each linker region |
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* |
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*/ |
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#define ONCHIP_FLASH_0_DATA_REGION_BASE 0x20 |
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#define ONCHIP_FLASH_0_DATA_REGION_SPAN 753632 |
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#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_BASE 0x400000 |
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#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_SPAN 32 |
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#define ONCHIP_MEMORY2_0_REGION_BASE 0x400020 |
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#define ONCHIP_MEMORY2_0_REGION_SPAN 262112 |
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#define RESET_REGION_BASE 0x0 |
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#define RESET_REGION_SPAN 32 |
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/*
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* Devices associated with code sections |
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* |
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*/ |
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#define ALT_EXCEPTIONS_DEVICE ONCHIP_MEMORY2_0 |
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#define ALT_RESET_DEVICE ONCHIP_FLASH_0_DATA |
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#define ALT_RODATA_DEVICE ONCHIP_MEMORY2_0 |
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#define ALT_RWDATA_DEVICE ONCHIP_MEMORY2_0 |
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#define ALT_TEXT_DEVICE ONCHIP_FLASH_0_DATA |
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/*
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* Initialization code at the reset address is allowed (e.g. no external bootloader). |
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* |
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*/ |
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#define ALT_ALLOW_CODE_AT_RESET |
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/*
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* The alt_load() facility is called from crt0 to copy sections into RAM. |
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* |
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*/ |
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#define ALT_LOAD_COPY_EXCEPTIONS |
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#define ALT_LOAD_COPY_RODATA |
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#define ALT_LOAD_COPY_RWDATA |
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#endif /* __LINKER_H_ */ |
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@ -1,281 +0,0 @@ |
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/*
|
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* DO NOT MODIFY THIS FILE |
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* |
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* Changing this file will have subtle consequences |
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* which will almost certainly lead to a nonfunctioning |
|
||||||
* system. If you do modify this file, be aware that your |
|
||||||
* changes will be overwritten and lost when this file |
|
||||||
* is generated again. |
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* |
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* DO NOT MODIFY THIS FILE |
|
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*/ |
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|
|
||||||
/*
|
|
||||||
* License Agreement |
|
||||||
* |
|
||||||
* Copyright (c) 2008 |
|
||||||
* Altera Corporation, San Jose, California, USA. |
|
||||||
* All rights reserved. |
|
||||||
* |
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a |
|
||||||
* copy of this software and associated documentation files (the "Software"), |
|
||||||
* to deal in the Software without restriction, including without limitation |
|
||||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
|
||||||
* and/or sell copies of the Software, and to permit persons to whom the |
|
||||||
* Software is furnished to do so, subject to the following conditions: |
|
||||||
* |
|
||||||
* The above copyright notice and this permission notice shall be included in |
|
||||||
* all copies or substantial portions of the Software. |
|
||||||
* |
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
|
||||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
|
||||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
|
||||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
|
||||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
|
||||||
* DEALINGS IN THE SOFTWARE. |
|
||||||
* |
|
||||||
* This agreement shall be governed in all respects by the laws of the State |
|
||||||
* of California and by the laws of the United States of America. |
|
||||||
*/ |
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|
|
||||||
#ifndef __SYSTEM_H_ |
|
||||||
#define __SYSTEM_H_ |
|
||||||
|
|
||||||
#include "linker.h" |
|
||||||
|
|
||||||
/*
|
|
||||||
* CPU configuration |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2" |
|
||||||
#define ALT_CPU_BIG_ENDIAN 0 |
|
||||||
#define ALT_CPU_BREAK_ADDR 0x00200820 |
|
||||||
#define ALT_CPU_CPU_ARCH_NIOS2_R1 |
|
||||||
#define ALT_CPU_CPU_FREQ 50000000u |
|
||||||
#define ALT_CPU_CPU_ID_SIZE 1 |
|
||||||
#define ALT_CPU_CPU_ID_VALUE 0x00000000 |
|
||||||
#define ALT_CPU_CPU_IMPLEMENTATION "tiny" |
|
||||||
#define ALT_CPU_DATA_ADDR_WIDTH 0x17 |
|
||||||
#define ALT_CPU_DCACHE_LINE_SIZE 0 |
|
||||||
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0 |
|
||||||
#define ALT_CPU_DCACHE_SIZE 0 |
|
||||||
#define ALT_CPU_EXCEPTION_ADDR 0x00400020 |
|
||||||
#define ALT_CPU_FLASH_ACCELERATOR_LINES 0 |
|
||||||
#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0 |
|
||||||
#define ALT_CPU_FLUSHDA_SUPPORTED |
|
||||||
#define ALT_CPU_FREQ 50000000 |
|
||||||
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 1 |
|
||||||
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1 |
|
||||||
#define ALT_CPU_HARDWARE_MULX_PRESENT 1 |
|
||||||
#define ALT_CPU_HAS_DEBUG_CORE 1 |
|
||||||
#define ALT_CPU_HAS_DEBUG_STUB |
|
||||||
#define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION |
|
||||||
#define ALT_CPU_HAS_JMPI_INSTRUCTION |
|
||||||
#define ALT_CPU_ICACHE_LINE_SIZE 0 |
|
||||||
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0 |
|
||||||
#define ALT_CPU_ICACHE_SIZE 0 |
|
||||||
#define ALT_CPU_INST_ADDR_WIDTH 0x17 |
|
||||||
#define ALT_CPU_NAME "nios2_gen2_0" |
|
||||||
#define ALT_CPU_OCI_VERSION 1 |
|
||||||
#define ALT_CPU_RESET_ADDR 0x00000000 |
|
||||||
#define ALT_CPU_HAS_EXTRA_EXCEPTION_INFO 1 |
|
||||||
|
|
||||||
|
|
||||||
#define ALT_DEVICE_FAMILY "MAX 10" |
|
||||||
#define ALT_ENHANCED_INTERRUPT_API_PRESENT |
|
||||||
#define ALT_IRQ_BASE NULL |
|
||||||
#define ALT_LOG_PORT "/dev/null" |
|
||||||
#define ALT_LOG_PORT_BASE 0x0 |
|
||||||
#define ALT_LOG_PORT_DEV null |
|
||||||
#define ALT_LOG_PORT_TYPE "" |
|
||||||
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0 |
|
||||||
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 |
|
||||||
#define ALT_NUM_INTERRUPT_CONTROLLERS 1 |
|
||||||
#define ALT_STDERR "/dev/jtag_uart_0" |
|
||||||
#define ALT_STDERR_BASE 0x201000 |
|
||||||
#define ALT_STDERR_DEV jtag_uart_0 |
|
||||||
#define ALT_STDERR_IS_JTAG_UART |
|
||||||
#define ALT_STDERR_PRESENT |
|
||||||
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart" |
|
||||||
#define ALT_STDIN "/dev/jtag_uart_0" |
|
||||||
#define ALT_STDIN_BASE 0x201000 |
|
||||||
#define ALT_STDIN_DEV jtag_uart_0 |
|
||||||
#define ALT_STDIN_IS_JTAG_UART |
|
||||||
#define ALT_STDIN_PRESENT |
|
||||||
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart" |
|
||||||
#define ALT_STDOUT "/dev/jtag_uart_0" |
|
||||||
#define ALT_STDOUT_BASE 0x201000 |
|
||||||
#define ALT_STDOUT_DEV jtag_uart_0 |
|
||||||
#define ALT_STDOUT_IS_JTAG_UART |
|
||||||
#define ALT_STDOUT_PRESENT |
|
||||||
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart" |
|
||||||
#define ALT_SYSTEM_NAME "ghrd_10m50da" |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* a_16550_uart_0 configuration |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define ALT_MODULE_CLASS_a_16550_uart_0 altera_16550_uart |
|
||||||
#define A_16550_UART_0_BASE 0x440000 |
|
||||||
#define A_16550_UART_0_FIFO_DEPTH 64 |
|
||||||
#define A_16550_UART_0_FIFO_MODE 1 |
|
||||||
#define A_16550_UART_0_FIO_HWFC 0 |
|
||||||
#define A_16550_UART_0_FIO_SWFC 0 |
|
||||||
#define A_16550_UART_0_FREQ 50000000 |
|
||||||
#define A_16550_UART_0_IRQ 1 |
|
||||||
#define A_16550_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 |
|
||||||
#define A_16550_UART_0_NAME "/dev/a_16550_uart_0" |
|
||||||
#define A_16550_UART_0_SPAN 512 |
|
||||||
#define A_16550_UART_0_TYPE "altera_16550_uart" |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* hal configuration |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API |
|
||||||
#define ALT_MAX_FD 32 |
|
||||||
#define ALT_SYS_CLK none |
|
||||||
#define ALT_TIMESTAMP_CLK none |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* jtag_uart_0 configuration |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart |
|
||||||
#define JTAG_UART_0_BASE 0x201000 |
|
||||||
#define JTAG_UART_0_IRQ 0 |
|
||||||
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 |
|
||||||
#define JTAG_UART_0_NAME "/dev/jtag_uart_0" |
|
||||||
#define JTAG_UART_0_READ_DEPTH 64 |
|
||||||
#define JTAG_UART_0_READ_THRESHOLD 8 |
|
||||||
#define JTAG_UART_0_SPAN 8 |
|
||||||
#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart" |
|
||||||
#define JTAG_UART_0_WRITE_DEPTH 64 |
|
||||||
#define JTAG_UART_0_WRITE_THRESHOLD 8 |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* onchip_flash_0_csr configuration |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define ALT_MODULE_CLASS_onchip_flash_0_csr altera_onchip_flash |
|
||||||
#define ONCHIP_FLASH_0_CSR_BASE 0x200000 |
|
||||||
#define ONCHIP_FLASH_0_CSR_BYTES_PER_PAGE 8192 |
|
||||||
#define ONCHIP_FLASH_0_CSR_IRQ -1 |
|
||||||
#define ONCHIP_FLASH_0_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1 |
|
||||||
#define ONCHIP_FLASH_0_CSR_NAME "/dev/onchip_flash_0_csr" |
|
||||||
#define ONCHIP_FLASH_0_CSR_READ_ONLY_MODE 0 |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR1_ENABLED 1 |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR1_END_ADDR 0x7fff |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR1_START_ADDR 0 |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR2_ENABLED 1 |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR2_END_ADDR 0xffff |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR2_START_ADDR 0x8000 |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR3_ENABLED 1 |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR3_END_ADDR 0x6ffff |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR3_START_ADDR 0x10000 |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR4_ENABLED 1 |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR4_END_ADDR 0xb7fff |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR4_START_ADDR 0x70000 |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR5_ENABLED 0 |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR5_END_ADDR 0xffffffff |
|
||||||
#define ONCHIP_FLASH_0_CSR_SECTOR5_START_ADDR 0xffffffff |
|
||||||
#define ONCHIP_FLASH_0_CSR_SPAN 8 |
|
||||||
#define ONCHIP_FLASH_0_CSR_TYPE "altera_onchip_flash" |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* onchip_flash_0_data configuration |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define ALT_MODULE_CLASS_onchip_flash_0_data altera_onchip_flash |
|
||||||
#define ONCHIP_FLASH_0_DATA_BASE 0x0 |
|
||||||
#define ONCHIP_FLASH_0_DATA_BYTES_PER_PAGE 8192 |
|
||||||
#define ONCHIP_FLASH_0_DATA_IRQ -1 |
|
||||||
#define ONCHIP_FLASH_0_DATA_IRQ_INTERRUPT_CONTROLLER_ID -1 |
|
||||||
#define ONCHIP_FLASH_0_DATA_NAME "/dev/onchip_flash_0_data" |
|
||||||
#define ONCHIP_FLASH_0_DATA_READ_ONLY_MODE 0 |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR1_ENABLED 1 |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR1_END_ADDR 0x7fff |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR1_START_ADDR 0 |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR2_ENABLED 1 |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR2_END_ADDR 0xffff |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR2_START_ADDR 0x8000 |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR3_ENABLED 1 |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR3_END_ADDR 0x6ffff |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR3_START_ADDR 0x10000 |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR4_ENABLED 1 |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR4_END_ADDR 0xb7fff |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR4_START_ADDR 0x70000 |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR5_ENABLED 0 |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR5_END_ADDR 0xffffffff |
|
||||||
#define ONCHIP_FLASH_0_DATA_SECTOR5_START_ADDR 0xffffffff |
|
||||||
#define ONCHIP_FLASH_0_DATA_SPAN 753664 |
|
||||||
#define ONCHIP_FLASH_0_DATA_TYPE "altera_onchip_flash" |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* onchip_memory2_0 configuration |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define ALT_MODULE_CLASS_onchip_memory2_0 altera_avalon_onchip_memory2 |
|
||||||
#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 |
|
||||||
#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 |
|
||||||
#define ONCHIP_MEMORY2_0_BASE 0x400000 |
|
||||||
#define ONCHIP_MEMORY2_0_CONTENTS_INFO "" |
|
||||||
#define ONCHIP_MEMORY2_0_DUAL_PORT 0 |
|
||||||
#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "AUTO" |
|
||||||
#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE "ghrd_10m50da_onchip_memory2_0" |
|
||||||
#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 0 |
|
||||||
#define ONCHIP_MEMORY2_0_INSTANCE_ID "NONE" |
|
||||||
#define ONCHIP_MEMORY2_0_IRQ -1 |
|
||||||
#define ONCHIP_MEMORY2_0_IRQ_INTERRUPT_CONTROLLER_ID -1 |
|
||||||
#define ONCHIP_MEMORY2_0_NAME "/dev/onchip_memory2_0" |
|
||||||
#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0 |
|
||||||
#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE "AUTO" |
|
||||||
#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE" |
|
||||||
#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0 |
|
||||||
#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1 |
|
||||||
#define ONCHIP_MEMORY2_0_SIZE_VALUE 262144 |
|
||||||
#define ONCHIP_MEMORY2_0_SPAN 262144 |
|
||||||
#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2" |
|
||||||
#define ONCHIP_MEMORY2_0_WRITABLE 1 |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* timer_0 configuration |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer |
|
||||||
#define TIMER_0_ALWAYS_RUN 0 |
|
||||||
#define TIMER_0_BASE 0x440200 |
|
||||||
#define TIMER_0_COUNTER_SIZE 32 |
|
||||||
#define TIMER_0_FIXED_PERIOD 0 |
|
||||||
#define TIMER_0_FREQ 50000000 |
|
||||||
#define TIMER_0_IRQ 2 |
|
||||||
#define TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID 0 |
|
||||||
#define TIMER_0_LOAD_VALUE 49999 |
|
||||||
#define TIMER_0_MULT 0.001 |
|
||||||
#define TIMER_0_NAME "/dev/timer_0" |
|
||||||
#define TIMER_0_PERIOD 1 |
|
||||||
#define TIMER_0_PERIOD_UNITS "ms" |
|
||||||
#define TIMER_0_RESET_OUTPUT 0 |
|
||||||
#define TIMER_0_SNAPSHOT 1 |
|
||||||
#define TIMER_0_SPAN 32 |
|
||||||
#define TIMER_0_TICKS_PER_SEC 1000 |
|
||||||
#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0 |
|
||||||
#define TIMER_0_TYPE "altera_avalon_timer" |
|
||||||
|
|
||||||
#endif /* __SYSTEM_H_ */ |
|
||||||
@ -1,20 +0,0 @@ |
|||||||
/* |
|
||||||
* Copyright (c) 2016 Intel Corporation |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: Apache-2.0 |
|
||||||
*/ |
|
||||||
|
|
||||||
/** |
|
||||||
* @brief Linker script for the Nios II/e CPU with timer and 16550 UART |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <layout.h> |
|
||||||
#include <zephyr/devicetree.h> |
|
||||||
|
|
||||||
#define _RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) |
|
||||||
#define _RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) |
|
||||||
|
|
||||||
#define _ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) |
|
||||||
#define _ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) |
|
||||||
|
|
||||||
#include <zephyr/arch/nios2/linker.ld> |
|
||||||
@ -1,13 +0,0 @@ |
|||||||
/*
|
|
||||||
* Copyright (c) 2018 Intel Corporation |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: Apache-2.0 |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
#ifndef __SOC_H_ |
|
||||||
#define __SOC_H_ |
|
||||||
|
|
||||||
#include <system.h> |
|
||||||
|
|
||||||
#endif |
|
||||||
Loading…
Reference in new issue