soc: neorv32: Port to HWMv2

Ports the SoC configuration to hardware model version 2 Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
1 year ago · d1edcdd088
10 changed files with 24 additions and 18 deletions
--- a/soc/soc_legacy/riscv/neorv32/CMakeLists.txt
+++ b/soc/soc_legacy/riscv/neorv32/CMakeLists.txt
--- a/soc/soc_legacy/riscv/neorv32/Kconfig.soc
+++ b/soc/soc_legacy/riscv/neorv32/Kconfig.soc
@ -2,7 +2,6 @@
 # SPDX-License-Identifier: Apache-2.0
 config SOC_NEORV32
 	bool "NEORV32 Processor"
 	select RISCV
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_M
@ -10,20 +9,6 @@ config SOC_NEORV32
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_PRIVILEGED
 	help
 	  Enable support for the NEORV32 Processor (SoC).
 	  The NEORV32 CPU implementation must have the following RISC-V ISA
 	  extensions enabled in order to support Zephyr:
 	  - M (Integer Multiplication and Division)
 	  - Zicsr (Control and Status Register (CSR) Instructions)
 	  The following NEORV32 CPU ISA extensions are not currently supported
 	  by Zephyr and can safely be disabled:
 	  - A (Atomic Instructions)
 	  - E (Embedded, only 16 integer registers)
 	  - Zbb (Basic Bit Manipulation)
 	  - Zfinx (Floating Point in Integer Registers)
 if SOC_NEORV32
--- a/soc/soc_legacy/riscv/neorv32/Kconfig.defconfig
+++ b/soc/soc_legacy/riscv/neorv32/Kconfig.defconfig
@ -3,9 +3,6 @@
 if SOC_NEORV32
 config SOC
 	default "neorv32"
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if RISCV_MACHINE_TIMER
--- a/soc/neorv32/Kconfig.soc
+++ b/soc/neorv32/Kconfig.soc
@ -0,0 +1,22 @@
 # Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
 # SPDX-License-Identifier: Apache-2.0
 config SOC_NEORV32
 	bool
 	help
 	  NEORV32 Processor (SoC).
 	  The NEORV32 CPU implementation must have the following RISC-V ISA
 	  extensions enabled in order to support Zephyr:
 	  - M (Integer Multiplication and Division)
 	  - Zicsr (Control and Status Register (CSR) Instructions)
 	  The following NEORV32 CPU ISA extensions are not currently supported
 	  by Zephyr and can safely be disabled:
 	  - A (Atomic Instructions)
 	  - E (Embedded, only 16 integer registers)
 	  - Zbb (Basic Bit Manipulation)
 	  - Zfinx (Floating Point in Integer Registers)
 config SOC
 	default "neorv32" if SOC_NEORV32
--- a/soc/soc_legacy/riscv/neorv32/linker.ld
+++ b/soc/soc_legacy/riscv/neorv32/linker.ld
--- a/soc/soc_legacy/riscv/neorv32/reset.S
+++ b/soc/soc_legacy/riscv/neorv32/reset.S
--- a/soc/soc_legacy/riscv/neorv32/soc.c
+++ b/soc/soc_legacy/riscv/neorv32/soc.c
--- a/soc/soc_legacy/riscv/neorv32/soc.h
+++ b/soc/soc_legacy/riscv/neorv32/soc.h
--- a/soc/neorv32/soc.yml
+++ b/soc/neorv32/soc.yml
@ -0,0 +1,2 @@
 socs:
  - name: neorv32
--- a/soc/soc_legacy/riscv/neorv32/soc_irq.S
+++ b/soc/soc_legacy/riscv/neorv32/soc_irq.S