diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa
index 29fc8cf9225..0b81ce5dd3a 100644
--- a/arch/riscv/Kconfig.isa
+++ b/arch/riscv/Kconfig.isa
@@ -34,7 +34,7 @@ config RISCV_ISA_EXT_M
 config RISCV_ISA_EXT_A
 	bool
 	imply RISCV_ISA_EXT_ZAAMO
-	imply RISCV_ISA_EXT_ZLRSC
+	imply RISCV_ISA_EXT_ZALRSC
 	help
 	  (A) - Standard Extension for Atomic Instructions
 
@@ -120,12 +120,12 @@ config RISCV_ISA_EXT_ZAAMO
 
 	  The Zaamo extension enables support for AMO*.W/D-style instructions.
 
-config RISCV_ISA_EXT_ZLRSC
+config RISCV_ISA_EXT_ZALRSC
 	bool
 	help
-	  (Zlrsc) - Load-Reserved/Store-Conditional subset of the A extension
+	  (Zalrsc) - Load-Reserved/Store-Conditional subset of the A extension
 
-	  The Zlrsc extension enables support for LR.W/D and SC.W/D-style instructions.
+	  The Zalrsc extension enables support for LR.W/D and SC.W/D-style instructions.
 
 config RISCV_ISA_EXT_ZBA
 	bool
diff --git a/cmake/compiler/gcc/target_riscv.cmake b/cmake/compiler/gcc/target_riscv.cmake
index 00a33fe3834..ccfc4df4f52 100644
--- a/cmake/compiler/gcc/target_riscv.cmake
+++ b/cmake/compiler/gcc/target_riscv.cmake
@@ -54,15 +54,15 @@ if(CONFIG_RISCV_ISA_EXT_ZIFENCEI)
   string(CONCAT riscv_march ${riscv_march} "_zifencei")
 endif()
 
-# Check whether we already imply Zaamo/Zlrsc by selecting the A extension; if not - check them
+# Check whether we already imply Zaamo/Zalrsc by selecting the A extension; if not - check them
 # individually and enable them as needed
 if(NOT CONFIG_RISCV_ISA_EXT_A)
   if(CONFIG_RISCV_ISA_EXT_ZAAMO)
     string(CONCAT riscv_march ${riscv_march} "_zaamo")
   endif()
 
-  if(CONFIG_RISCV_ISA_EXT_ZLRSC)
-    string(CONCAT riscv_march ${riscv_march} "_zlrsc")
+  if(CONFIG_RISCV_ISA_EXT_ZALRSC)
+    string(CONCAT riscv_march ${riscv_march} "_zalrsc")
   endif()
 endif()