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@ -357,8 +357,8 @@ static const struct clock_control_driver_api clock_control_esp32_api = {
@@ -357,8 +357,8 @@ static const struct clock_control_driver_api clock_control_esp32_api = {
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}; |
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static const struct esp32_clock_config esp32_clock_config0 = { |
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.clk_src_sel = DT_PROP(DT_INST(0, cadence_tensilica_xtensa_lx6), clock_source), |
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.cpu_freq = DT_PROP(DT_INST(0, cadence_tensilica_xtensa_lx6), clock_frequency), |
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.clk_src_sel = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_source), |
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.cpu_freq = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_frequency), |
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.xtal_freq_sel = DT_INST_PROP(0, xtal_freq), |
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.xtal_div = DT_INST_PROP(0, xtal_div), |
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}; |
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@ -370,8 +370,9 @@ DEVICE_DT_INST_DEFINE(0,
@@ -370,8 +370,9 @@ DEVICE_DT_INST_DEFINE(0,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, |
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&clock_control_esp32_api); |
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BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) == MHZ(DT_PROP(DT_INST(0, cadence_tensilica_xtensa_lx6), clock_frequency)), |
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"SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq"); |
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BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) == |
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MHZ(DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_frequency)), |
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"SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq"); |
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BUILD_ASSERT(DT_NODE_HAS_PROP(DT_INST(0, cadence_tensilica_xtensa_lx6), clock_source), |
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BUILD_ASSERT(DT_NODE_HAS_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_source), |
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"CPU clock-source property must be set to ESP32_CLK_SRC_XTAL or ESP32_CLK_SRC_PLL"); |
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