From cd42555ea660707633610f472de841fb5dd4deff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Karol=20Laso=C5=84czyk?= Date: Tue, 1 Jul 2025 10:56:11 +0200 Subject: [PATCH] snippets: nordic-flpr: Fix nRF54LM20A memory layout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes wrongly set memory space for FLPR core. Signed-off-by: Karol Lasończyk --- .../nordic-flpr/soc/nrf54lm20a_cpuapp.overlay | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/snippets/nordic-flpr/soc/nrf54lm20a_cpuapp.overlay b/snippets/nordic-flpr/soc/nrf54lm20a_cpuapp.overlay index 1d36ba5ac48..071241cf03d 100644 --- a/snippets/nordic-flpr/soc/nrf54lm20a_cpuapp.overlay +++ b/snippets/nordic-flpr/soc/nrf54lm20a_cpuapp.overlay @@ -9,22 +9,27 @@ #address-cells = <1>; #size-cells = <1>; - cpuflpr_code_partition: image@1ed000 { + cpuflpr_code_partition: image@1e5000 { /* FLPR core code partition */ - reg = <0x1ed000 DT_SIZE_K(64)>; + reg = <0x1e5000 DT_SIZE_K(96)>; }; }; - cpuflpr_sram_code_data: memory@2006fc00 { + cpuflpr_sram_code_data: memory@20067c00 { compatible = "mmio-sram"; - reg = <0x2006fc00 DT_SIZE_K(64)>; + reg = <0x20067c00 DT_SIZE_K(96)>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x2006fc00 0x10000>; + ranges = <0x0 0x20067c00 DT_SIZE_K(96)>; }; }; }; +&cpuapp_sram { + reg = <0x20000000 DT_SIZE_K(415)>; + ranges = <0x0 0x20000000 DT_SIZE_K(415)>; +}; + &uart30 { status = "reserved"; };