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soc: xlnx: zynq7000: add FPU support

According to its datasheet the Zynq 7000 has a VFPv3 FPU

Signed-off-by: Simon Maurer <mail@maurer.systems>
pull/90956/merge
Simon Maurer 6 months ago committed by Daniel DeGrasse
parent
commit
cb982d16ef
  1. 12
      arch/arm/core/Kconfig.vfp
  2. 8
      cmake/gcc-m-fpu.cmake
  3. 1
      soc/xlnx/zynq7000/xc7zxxx/Kconfig
  4. 1
      soc/xlnx/zynq7000/xc7zxxxs/Kconfig

12
arch/arm/core/Kconfig.vfp

@ -109,6 +109,18 @@ config VFP_U_DP_D16_FP16_FMAC @@ -109,6 +109,18 @@ config VFP_U_DP_D16_FP16_FMAC
fused multiply-accumulate) and floating-point exception trapping with 16
double-word registers.
config VFP_DP_D32_FMAC
bool
select CPU_HAS_VFP
select VFP_FEATURE_SINGLE_PRECISION
select VFP_FEATURE_DOUBLE_PRECISION
select VFP_FEATURE_FMAC
select VFP_FEATURE_REGS_S64_D32
help
This option signifies the use of a VFP floating-point coprocessor
that supports single- and double-precision operations
(including fused multiply-accumulate) with 32 double-word registers.
config VFP_DP_D32_FP16_FMAC
bool
select CPU_HAS_VFP

8
cmake/gcc-m-fpu.cmake

@ -48,6 +48,14 @@ if("${ARCH}" STREQUAL "arm") @@ -48,6 +48,14 @@ if("${ARCH}" STREQUAL "arm")
elseif(CONFIG_CPU_AARCH32_CORTEX_A)
if(CONFIG_CPU_CORTEX_A7)
set(GCC_M_FPU vfpv4-d16)
elseif(CONFIG_CPU_CORTEX_A9)
set(GCC_M_FPU vfpv3)
if(NOT CONFIG_VFP_FEATURE_REGS_S64_D32)
set(GCC_M_FPU ${GCC_M_FPU}-d16)
endif()
if(CONFIG_VFP_FEATURE_HALF_PRECISION)
set(GCC_M_FPU ${GCC_M_FPU}-fp16)
endif()
endif()
endif()
endif()

1
soc/xlnx/zynq7000/xc7zxxx/Kconfig

@ -11,3 +11,4 @@ config SOC_SERIES_XC7ZXXX @@ -11,3 +11,4 @@ config SOC_SERIES_XC7ZXXX
select CPU_CORTEX_A9
select SYSCON
select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
select VFP_DP_D32_FMAC

1
soc/xlnx/zynq7000/xc7zxxxs/Kconfig

@ -11,3 +11,4 @@ config SOC_SERIES_XC7ZXXXS @@ -11,3 +11,4 @@ config SOC_SERIES_XC7ZXXXS
select CPU_CORTEX_A9
select SYSCON
select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
select VFP_DP_D32_FMAC

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