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@ -12,10 +12,10 @@
@@ -12,10 +12,10 @@
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#include <zephyr/drivers/gpio/gpio_utils.h> |
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#include <zephyr/drivers/mfd/npm13xx.h> |
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#define TIME_BASE 0x07U |
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#define MAIN_BASE 0x00U |
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#define SHIP_BASE 0x0BU |
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#define GPIO_BASE 0x06U |
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#define NPM13XX_TIME_BASE 0x07U |
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#define NPM13XX_MAIN_BASE 0x00U |
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#define NPM13XX_SHIP_BASE 0x0BU |
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#define NPM13XX_GPIO_BASE 0x06U |
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#define TIME_OFFSET_LOAD 0x03U |
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#define TIME_OFFSET_TIMER 0x08U |
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@ -93,7 +93,7 @@ static void work_callback(struct k_work *work)
@@ -93,7 +93,7 @@ static void work_callback(struct k_work *work)
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int ret; |
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/* Read all MAIN registers into temporary buffer */ |
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ret = mfd_npm13xx_reg_read_burst(data->dev, MAIN_BASE, 0U, buf, sizeof(buf)); |
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ret = mfd_npm13xx_reg_read_burst(data->dev, NPM13XX_MAIN_BASE, 0U, buf, sizeof(buf)); |
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if (ret < 0) { |
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k_work_submit(&data->work); |
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return; |
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@ -105,7 +105,7 @@ static void work_callback(struct k_work *work)
@@ -105,7 +105,7 @@ static void work_callback(struct k_work *work)
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if ((buf[offset] & event_reg[i].mask) != 0U) { |
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gpio_fire_callbacks(&data->callbacks, data->dev, BIT(i)); |
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ret = mfd_npm13xx_reg_write(data->dev, MAIN_BASE, offset, |
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ret = mfd_npm13xx_reg_write(data->dev, NPM13XX_MAIN_BASE, offset, |
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event_reg[i].mask); |
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if (ret < 0) { |
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k_work_submit(&data->work); |
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@ -136,7 +136,8 @@ static int mfd_npm13xx_init(const struct device *dev)
@@ -136,7 +136,8 @@ static int mfd_npm13xx_init(const struct device *dev)
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if (config->host_int_gpios.port != NULL) { |
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/* Set specified PMIC pin to be interrupt output */ |
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ret = mfd_npm13xx_reg_write(dev, GPIO_BASE, GPIO_OFFSET_MODE + config->pmic_int_pin, |
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ret = mfd_npm13xx_reg_write(dev, NPM13XX_GPIO_BASE, |
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GPIO_OFFSET_MODE + config->pmic_int_pin, |
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GPIO_MODE_GPOIRQ); |
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if (ret < 0) { |
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return ret; |
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@ -169,17 +170,18 @@ static int mfd_npm13xx_init(const struct device *dev)
@@ -169,17 +170,18 @@ static int mfd_npm13xx_init(const struct device *dev)
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} |
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} |
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ret = mfd_npm13xx_reg_write(dev, SHIP_BASE, SHIP_OFFSET_CONFIG, config->active_time); |
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ret = mfd_npm13xx_reg_write(dev, NPM13XX_SHIP_BASE, SHIP_OFFSET_CONFIG, |
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config->active_time); |
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if (ret < 0) { |
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return ret; |
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} |
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ret = mfd_npm13xx_reg_write(dev, SHIP_BASE, SHIP_OFFSET_LPCONFIG, config->lp_reset); |
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ret = mfd_npm13xx_reg_write(dev, NPM13XX_SHIP_BASE, SHIP_OFFSET_LPCONFIG, config->lp_reset); |
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if (ret < 0) { |
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return ret; |
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} |
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return mfd_npm13xx_reg_write(dev, SHIP_BASE, SHIP_OFFSET_CFGSTROBE, 1U); |
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return mfd_npm13xx_reg_write(dev, NPM13XX_SHIP_BASE, SHIP_OFFSET_CFGSTROBE, 1U); |
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} |
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int mfd_npm13xx_reg_read_burst(const struct device *dev, uint8_t base, uint8_t offset, void *data, |
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@ -237,7 +239,7 @@ int mfd_npm13xx_reg_update(const struct device *dev, uint8_t base, uint8_t offse
@@ -237,7 +239,7 @@ int mfd_npm13xx_reg_update(const struct device *dev, uint8_t base, uint8_t offse
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int mfd_npm13xx_set_timer(const struct device *dev, uint32_t time_ms) |
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{ |
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const struct mfd_npm13xx_config *config = dev->config; |
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uint8_t buff[5] = {TIME_BASE, TIME_OFFSET_TIMER}; |
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uint8_t buff[5] = {NPM13XX_TIME_BASE, TIME_OFFSET_TIMER}; |
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uint32_t ticks = time_ms / TIMER_PRESCALER_MS; |
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if (ticks > TIMER_MAX) { |
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@ -252,12 +254,12 @@ int mfd_npm13xx_set_timer(const struct device *dev, uint32_t time_ms)
@@ -252,12 +254,12 @@ int mfd_npm13xx_set_timer(const struct device *dev, uint32_t time_ms)
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return ret; |
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} |
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return mfd_npm13xx_reg_write(dev, TIME_BASE, TIME_OFFSET_LOAD, 1U); |
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return mfd_npm13xx_reg_write(dev, NPM13XX_TIME_BASE, TIME_OFFSET_LOAD, 1U); |
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} |
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int mfd_npm13xx_reset(const struct device *dev) |
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{ |
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return mfd_npm13xx_reg_write(dev, MAIN_BASE, MAIN_OFFSET_RESET, 1U); |
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return mfd_npm13xx_reg_write(dev, NPM13XX_MAIN_BASE, MAIN_OFFSET_RESET, 1U); |
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} |
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int mfd_npm13xx_hibernate(const struct device *dev, uint32_t time_ms) |
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@ -268,7 +270,7 @@ int mfd_npm13xx_hibernate(const struct device *dev, uint32_t time_ms)
@@ -268,7 +270,7 @@ int mfd_npm13xx_hibernate(const struct device *dev, uint32_t time_ms)
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return ret; |
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} |
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return mfd_npm13xx_reg_write(dev, SHIP_BASE, SHIP_OFFSET_HIBERNATE, 1U); |
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return mfd_npm13xx_reg_write(dev, NPM13XX_SHIP_BASE, SHIP_OFFSET_HIBERNATE, 1U); |
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} |
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int mfd_npm13xx_add_callback(const struct device *dev, struct gpio_callback *callback) |
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@ -279,7 +281,7 @@ int mfd_npm13xx_add_callback(const struct device *dev, struct gpio_callback *cal
@@ -279,7 +281,7 @@ int mfd_npm13xx_add_callback(const struct device *dev, struct gpio_callback *cal
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for (int i = 0; i < NPM13XX_EVENT_MAX; i++) { |
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if ((callback->pin_mask & BIT(i)) != 0U) { |
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/* Clear pending interrupt */ |
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int ret = mfd_npm13xx_reg_write(data->dev, MAIN_BASE, |
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int ret = mfd_npm13xx_reg_write(data->dev, NPM13XX_MAIN_BASE, |
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event_reg[i].offset + MAIN_OFFSET_CLR, |
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event_reg[i].mask); |
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@ -287,7 +289,7 @@ int mfd_npm13xx_add_callback(const struct device *dev, struct gpio_callback *cal
@@ -287,7 +289,7 @@ int mfd_npm13xx_add_callback(const struct device *dev, struct gpio_callback *cal
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return ret; |
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} |
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ret = mfd_npm13xx_reg_write(data->dev, MAIN_BASE, |
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ret = mfd_npm13xx_reg_write(data->dev, NPM13XX_MAIN_BASE, |
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event_reg[i].offset + MAIN_OFFSET_INTENSET, |
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event_reg[i].mask); |
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if (ret < 0) { |
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