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The nRF54L15 Development Kit is now available, so remove the Preview Development Kit (PDK). Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>pull/80118/head
Carles Cufi
9 months ago
committed by
David Leach
75 changed files with 3 additions and 1598 deletions
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# Copyright (c) 2024 Nordic Semiconductor ASA |
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# SPDX-License-Identifier: Apache-2.0 |
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if BOARD_NRF54L15PDK_NRF54L15_CPUAPP |
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config BT_CTLR |
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default BT |
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config ROM_START_OFFSET |
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default 0x800 if BOOTLOADER_MCUBOOT |
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endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP |
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# Copyright (c) 2024 Nordic Semiconductor ASA |
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# SPDX-License-Identifier: Apache-2.0 |
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config BOARD_NRF54L15PDK |
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select SOC_NRF54L15_ENGA_CPUAPP if BOARD_NRF54L15PDK_NRF54L15_CPUAPP |
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select SOC_NRF54L15_ENGA_CPUFLPR if BOARD_NRF54L15PDK_NRF54L15_CPUFLPR || \ |
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BOARD_NRF54L15PDK_NRF54L15_CPUFLPR_XIP |
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# Copyright (c) 2024 Nordic Semiconductor ASA |
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# SPDX-License-Identifier: Apache-2.0 |
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if (CONFIG_SOC_NRF54L15_ENGA_CPUAPP) |
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board_runner_args(jlink "--device=cortex-m33" "--speed=4000") |
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elseif (CONFIG_SOC_NRF54L15_ENGA_CPUFLPR) |
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board_runner_args(jlink "--speed=4000") |
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endif() |
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include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) |
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include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) |
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) |
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board: |
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name: nrf54l15pdk |
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full_name: nRF54L15 PDK |
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vendor: nordic |
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socs: |
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- name: nrf54l15 |
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variants: |
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- name: xip |
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cpucluster: cpuflpr |
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revision: |
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format: major.minor.patch |
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default: "0.3.0" |
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revisions: |
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- name: "0.2.1" |
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- name: "0.3.0" |
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Before Width: | Height: | Size: 35 KiB |
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.. _nrf54l15pdk_nrf54l15: |
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nRF54L15 PDK |
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############ |
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Overview |
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******** |
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.. note:: |
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All software for the nRF54L15 SoC is experimental and hardware availability |
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is restricted to the participants in the limited sampling program. |
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|
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The nRF54L15 Preview Development Kit hardware provides |
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support for the Nordic Semiconductor nRF54L15 Arm Cortex-M33 CPU and |
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the following devices: |
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* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)` |
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* CLOCK |
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* RRAM |
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* :abbr:`GPIO (General Purpose Input Output)` |
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* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)` |
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* MEMCONF |
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* :abbr:`MPU (Memory Protection Unit)` |
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* :abbr:`NVIC (Nested Vectored Interrupt Controller)` |
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* :abbr:`PWM (Pulse Width Modulation)` |
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* :abbr:`GRTC (Global real-time counter)` |
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* Segger RTT (RTT Console) |
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* :abbr:`SPI (Serial Peripheral Interface)` |
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* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` |
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* :abbr:`WDT (Watchdog Timer)` |
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|
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.. figure:: img/nrf54l15pdk_nrf54l15.webp |
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:align: center |
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:alt: nRF54L15 PDK |
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|
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nRF54L15 PDK (Credit: Nordic Semiconductor) |
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Hardware |
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******** |
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|
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nRF54L15 PDK has two crystal oscillators: |
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* High-frequency 32 MHz crystal oscillator (HFXO) |
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* Low-frequency 32.768 kHz crystal oscillator (LFXO) |
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The crystal oscillators can be configured to use either |
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internal or external capacitors. |
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Supported Features |
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================== |
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|
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The ``nrf54l15pdk/nrf54l15/cpuapp`` board configuration supports the following |
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hardware features: |
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+-----------+------------+----------------------+ |
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| Interface | Controller | Driver/Component | |
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+===========+============+======================+ |
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| SAADC | on-chip | adc | |
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+-----------+------------+----------------------+ |
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| CLOCK | on-chip | clock_control | |
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+-----------+------------+----------------------+ |
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| RRAM | on-chip | flash | |
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+-----------+------------+----------------------+ |
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| GPIO | on-chip | gpio | |
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+-----------+------------+----------------------+ |
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| TWIM | on-chip | i2c | |
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+-----------+------------+----------------------+ |
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| MEMCONF | on-chip | retained_mem | |
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+-----------+------------+----------------------+ |
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| MPU | on-chip | arch/arm | |
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+-----------+------------+----------------------+ |
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| NVIC | on-chip | arch/arm | |
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+-----------+------------+----------------------+ |
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| PWM | on-chip | pwm | |
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+-----------+------------+----------------------+ |
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| GRTC | on-chip | counter | |
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+-----------+------------+----------------------+ |
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| RTT | Segger | console | |
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+-----------+------------+----------------------+ |
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| SPI(M/S) | on-chip | spi | |
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+-----------+------------+----------------------+ |
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| SPU | on-chip | system protection | |
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+-----------+------------+----------------------+ |
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| UARTE | on-chip | serial | |
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+-----------+------------+----------------------+ |
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| WDT | on-chip | watchdog | |
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+-----------+------------+----------------------+ |
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Other hardware features have not been enabled yet for this board. |
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Programming and Debugging |
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************************* |
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Applications for the ``nrf54l15pdk/nrf54l15/cpuapp`` board can be |
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built, flashed, and debugged in the usual way. See |
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:ref:`build_an_application` and :ref:`application_run` for more details on |
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building and running. |
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Flashing |
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======== |
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As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` |
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application. |
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.. warning:: |
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When programming the device, you might get an error similar to the following message:: |
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ERROR: The operation attempted is unavailable due to readback protection in |
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ERROR: your device. Please use --recover to unlock the device. |
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This error occurs when readback protection is enabled. |
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To disable the readback protection, you must *recover* your device. |
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Enter the following command to recover the core:: |
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west flash --recover |
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The ``--recover`` command erases the flash memory and then writes a small binary into |
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the recovered flash memory. |
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This binary prevents the readback protection from enabling itself again after a pin |
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reset or power cycle. |
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Follow the instructions in the :ref:`nordic_segger` page to install |
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and configure all the necessary software. Further information can be |
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found in :ref:`nordic_segger_flashing`. |
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To build and program the sample to the nRF54L15 PDK, complete the following steps: |
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First, connect the nRF54L15 PDK to you computer using the IMCU USB port on the PDK. |
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Next, build the sample by running the following command: |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: nrf54l15pdk/nrf54l15/cpuapp |
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:goals: build flash |
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Testing the LEDs and buttons in the nRF54L15 PDK |
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************************************************ |
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Test the nRF54L15 PDK with a :zephyr:code-sample:`blinky` sample. |
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@ -1,156 +0,0 @@
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/* |
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* Copyright (c) 2024 Nordic Semiconductor ASA |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/* This file is common to the secure and non-secure domain */ |
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#include <nordic/nrf54l15_enga_cpuapp.dtsi> |
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#include "nrf54l15pdk_nrf54l15-common.dtsi" |
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/ { |
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chosen { |
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zephyr,console = &uart20; |
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zephyr,shell-uart = &uart20; |
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zephyr,uart-mcumgr = &uart20; |
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zephyr,bt-mon-uart = &uart20; |
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zephyr,bt-c2h-uart = &uart20; |
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zephyr,flash-controller = &rram_controller; |
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zephyr,flash = &cpuapp_rram; |
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zephyr,ieee802154 = &ieee802154; |
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}; |
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}; |
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&cpuapp_sram { |
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status = "okay"; |
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}; |
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&lfxo { |
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load-capacitors = "internal"; |
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load-capacitance-femtofarad = <15500>; |
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}; |
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&hfxo { |
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load-capacitors = "internal"; |
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load-capacitance-femtofarad = <15000>; |
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}; |
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®ulators { |
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status = "okay"; |
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}; |
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&vregmain { |
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status = "okay"; |
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regulator-initial-mode = <NRF5X_REG_MODE_DCDC>; |
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}; |
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&grtc { |
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owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; |
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/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ |
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child-owned-channels = <3 4 7 8 9 10 11>; |
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status = "okay"; |
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}; |
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&cpuapp_rram { |
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partitions { |
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compatible = "fixed-partitions"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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boot_partition: partition@0 { |
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label = "mcuboot"; |
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reg = <0x0 DT_SIZE_K(64)>; |
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}; |
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slot0_partition: partition@10000 { |
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label = "image-0"; |
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reg = <0x10000 DT_SIZE_K(324)>; |
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}; |
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slot0_ns_partition: partition@61000 { |
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label = "image-0-nonsecure"; |
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reg = <0x61000 DT_SIZE_K(324)>; |
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}; |
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slot1_partition: partition@b2000 { |
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label = "image-1"; |
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reg = <0xb2000 DT_SIZE_K(324)>; |
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}; |
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slot1_ns_partition: partition@103000 { |
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label = "image-1-nonsecure"; |
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reg = <0x103000 DT_SIZE_K(324)>; |
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}; |
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/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */ |
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storage_partition: partition@15c000 { |
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label = "storage"; |
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reg = <0x15c000 DT_SIZE_K(36)>; |
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}; |
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}; |
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}; |
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&uart20 { |
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status = "okay"; |
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}; |
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&gpio0 { |
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status = "okay"; |
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}; |
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&gpio1 { |
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status = "okay"; |
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}; |
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&gpio2 { |
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status = "okay"; |
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}; |
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&gpiote20 { |
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status = "okay"; |
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}; |
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&gpiote30 { |
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status = "okay"; |
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}; |
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&radio { |
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status = "okay"; |
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}; |
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&ieee802154 { |
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status = "okay"; |
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}; |
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&temp { |
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status = "okay"; |
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}; |
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&clock { |
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status = "okay"; |
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}; |
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&spi00 { |
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status = "okay"; |
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cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; |
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pinctrl-0 = <&spi00_default>; |
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pinctrl-1 = <&spi00_sleep>; |
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pinctrl-names = "default", "sleep"; |
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mx25r64: mx25r6435f@0 { |
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compatible = "jedec,spi-nor"; |
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status = "disabled"; |
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reg = <0>; |
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spi-max-frequency = <8000000>; |
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jedec-id = [c2 28 17]; |
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sfdp-bfp = [ |
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e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb |
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ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 |
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10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44 |
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30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff |
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]; |
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size = <67108864>; |
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has-dpd; |
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t-enter-dpd = <10000>; |
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t-exit-dpd = <35000>; |
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}; |
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}; |
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&adc { |
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status = "okay"; |
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}; |
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/* |
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* Copyright (c) 2024 Nordic Semiconductor ASA |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include "nrf54l15pdk_nrf54l15-pinctrl.dtsi" |
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/ { |
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leds { |
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compatible = "gpio-leds"; |
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led0: led_0 { |
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gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; |
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label = "Green LED 0"; |
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}; |
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led1: led_1 { |
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gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; |
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label = "Green LED 1"; |
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}; |
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led2: led_2 { |
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gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; |
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label = "Green LED 2"; |
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}; |
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led3: led_3 { |
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gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; |
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label = "Green LED 3"; |
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}; |
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}; |
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pwmleds { |
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compatible = "pwm-leds"; |
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/* |
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* PWM signal can be exposed on GPIO pin only within same domain. |
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* There is only one domain which contains both PWM and GPIO: |
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* PWM20/21/22 and GPIO Port P1. |
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* Only LEDs connected to P1 can work with PWM, for example LED1. |
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*/ |
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pwm_led1: pwm_led_1 { |
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pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; |
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}; |
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}; |
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buttons { |
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compatible = "gpio-keys"; |
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button0: button_0 { |
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gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; |
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label = "Push button 0"; |
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zephyr,code = <INPUT_KEY_0>; |
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}; |
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button1: button_1 { |
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gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; |
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label = "Push button 1"; |
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zephyr,code = <INPUT_KEY_1>; |
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}; |
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button2: button_2 { |
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gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; |
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label = "Push button 2"; |
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zephyr,code = <INPUT_KEY_2>; |
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}; |
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button3: button_3 { |
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gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; |
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label = "Push button 3"; |
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zephyr,code = <INPUT_KEY_3>; |
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}; |
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}; |
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aliases { |
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led0 = &led0; |
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led1 = &led1; |
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led2 = &led2; |
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led3 = &led3; |
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pwm-led0 = &pwm_led1; |
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sw0 = &button0; |
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sw1 = &button1; |
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sw2 = &button2; |
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sw3 = &button3; |
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watchdog0 = &wdt31; |
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}; |
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}; |
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|
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&uart20 { |
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current-speed = <115200>; |
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pinctrl-0 = <&uart20_default>; |
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pinctrl-1 = <&uart20_sleep>; |
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pinctrl-names = "default", "sleep"; |
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}; |
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|
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&uart30 { |
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current-speed = <115200>; |
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pinctrl-0 = <&uart30_default>; |
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pinctrl-1 = <&uart30_sleep>; |
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pinctrl-names = "default", "sleep"; |
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}; |
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|
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&pwm20 { |
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status = "okay"; |
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pinctrl-0 = <&pwm20_default>; |
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pinctrl-1 = <&pwm20_sleep>; |
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pinctrl-names = "default", "sleep"; |
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}; |
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@ -1,80 +0,0 @@
@@ -1,80 +0,0 @@
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/* |
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* Copyright (c) 2024 Nordic Semiconductor |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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|
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&pinctrl { |
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/omit-if-no-ref/ uart20_default: uart20_default { |
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group1 { |
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psels = <NRF_PSEL(UART_TX, 1, 4)>, |
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<NRF_PSEL(UART_RTS, 1, 6)>; |
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}; |
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group2 { |
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psels = <NRF_PSEL(UART_RX, 1, 5)>, |
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<NRF_PSEL(UART_CTS, 1, 7)>; |
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bias-pull-up; |
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}; |
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}; |
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|
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/omit-if-no-ref/ uart20_sleep: uart20_sleep { |
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group1 { |
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psels = <NRF_PSEL(UART_TX, 1, 4)>, |
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<NRF_PSEL(UART_RX, 1, 5)>, |
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<NRF_PSEL(UART_RTS, 1, 6)>, |
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<NRF_PSEL(UART_CTS, 1, 7)>; |
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low-power-enable; |
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}; |
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}; |
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|
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/omit-if-no-ref/ uart30_default: uart30_default { |
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group1 { |
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psels = <NRF_PSEL(UART_TX, 0, 0)>, |
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<NRF_PSEL(UART_RTS, 0, 2)>; |
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}; |
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group2 { |
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psels = <NRF_PSEL(UART_RX, 0, 1)>, |
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<NRF_PSEL(UART_CTS, 0, 3)>; |
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bias-pull-up; |
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}; |
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}; |
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|
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/omit-if-no-ref/ uart30_sleep: uart30_sleep { |
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group1 { |
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psels = <NRF_PSEL(UART_TX, 0, 0)>, |
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<NRF_PSEL(UART_RX, 0, 1)>, |
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<NRF_PSEL(UART_RTS, 0, 2)>, |
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<NRF_PSEL(UART_CTS, 0, 3)>; |
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low-power-enable; |
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}; |
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}; |
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|
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/omit-if-no-ref/ spi00_default: spi00_default { |
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group1 { |
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psels = <NRF_PSEL(SPIM_SCK, 2, 1)>, |
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<NRF_PSEL(SPIM_MOSI, 2, 2)>, |
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<NRF_PSEL(SPIM_MISO, 2, 4)>; |
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}; |
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}; |
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|
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/omit-if-no-ref/ spi00_sleep: spi00_sleep { |
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group1 { |
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psels = <NRF_PSEL(SPIM_SCK, 2, 1)>, |
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<NRF_PSEL(SPIM_MOSI, 2, 2)>, |
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<NRF_PSEL(SPIM_MISO, 2, 4)>; |
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low-power-enable; |
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}; |
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}; |
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|
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/omit-if-no-ref/ pwm20_default: pwm20_default { |
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group1 { |
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psels = <NRF_PSEL(PWM_OUT0, 1, 10)>; |
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}; |
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}; |
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|
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/omit-if-no-ref/ pwm20_sleep: pwm20_sleep { |
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group1 { |
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psels = <NRF_PSEL(PWM_OUT0, 1, 10)>; |
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low-power-enable; |
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}; |
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}; |
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}; |
||||
@ -1,52 +0,0 @@
@@ -1,52 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
&led0 { |
||||
gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; |
||||
}; |
||||
|
||||
&led1 { |
||||
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; |
||||
}; |
||||
|
||||
&led2 { |
||||
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; |
||||
}; |
||||
|
||||
&led3 { |
||||
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; |
||||
}; |
||||
|
||||
&button0 { |
||||
gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; |
||||
}; |
||||
|
||||
&button1 { |
||||
gpios = <&gpio1 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; |
||||
}; |
||||
|
||||
&button2 { |
||||
gpios = <&gpio2 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; |
||||
}; |
||||
|
||||
&button3 { |
||||
gpios = <&gpio2 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; |
||||
}; |
||||
|
||||
&pinctrl { |
||||
/omit-if-no-ref/ pwm20_default: pwm20_default { |
||||
group1 { |
||||
psels = <NRF_PSEL(PWM_OUT0, 1, 8)>; |
||||
}; |
||||
}; |
||||
|
||||
/omit-if-no-ref/ pwm20_sleep: pwm20_sleep { |
||||
group1 { |
||||
psels = <NRF_PSEL(PWM_OUT0, 1, 8)>; |
||||
low-power-enable; |
||||
}; |
||||
}; |
||||
}; |
||||
@ -1,19 +0,0 @@
@@ -1,19 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
|
||||
#include "nrf54l15_cpuapp_common.dtsi" |
||||
|
||||
/ { |
||||
compatible = "nordic,nrf54l15pdk_nrf54l15-cpuapp"; |
||||
model = "Nordic nRF54L15 PDK nRF54L15 Application MCU"; |
||||
|
||||
chosen { |
||||
zephyr,code-partition = &slot0_partition; |
||||
zephyr,sram = &cpuapp_sram; |
||||
}; |
||||
}; |
||||
@ -1,24 +0,0 @@
@@ -1,24 +0,0 @@
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
identifier: nrf54l15pdk/nrf54l15/cpuapp |
||||
name: nRF54l15-PDK-nRF54l15-Application |
||||
type: mcu |
||||
arch: arm |
||||
toolchain: |
||||
- gnuarmemb |
||||
- xtools |
||||
- zephyr |
||||
sysbuild: true |
||||
ram: 188 |
||||
flash: 324 |
||||
supported: |
||||
- adc |
||||
- counter |
||||
- gpio |
||||
- i2c |
||||
- pwm |
||||
- retained_mem |
||||
- spi |
||||
- watchdog |
||||
- i2s |
||||
@ -1,7 +0,0 @@
@@ -1,7 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
#include "nrf54l15pdk_nrf54l15_common_0_2_1.dtsi" |
||||
@ -1,31 +0,0 @@
@@ -1,31 +0,0 @@
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
# Enable UART driver |
||||
CONFIG_SERIAL=y |
||||
|
||||
# Enable console |
||||
CONFIG_CONSOLE=y |
||||
CONFIG_UART_CONSOLE=y |
||||
|
||||
# Enable GPIO |
||||
CONFIG_GPIO=y |
||||
|
||||
# Enable MPU |
||||
CONFIG_ARM_MPU=y |
||||
|
||||
# Enable hardware stack protection |
||||
CONFIG_HW_STACK_PROTECTION=y |
||||
|
||||
# MPU-based null-pointer dereferencing detection cannot |
||||
# be applied as the (0x0 - 0x400) is unmapped for this target. |
||||
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y |
||||
|
||||
# Enable Cache |
||||
CONFIG_CACHE_MANAGEMENT=y |
||||
CONFIG_EXTERNAL_CACHE=y |
||||
|
||||
CONFIG_SOC_NRF_FORCE_CONSTLAT=y |
||||
|
||||
# Start SYSCOUNTER on driver init |
||||
CONFIG_NRF_GRTC_START_SYSCOUNTER=y |
||||
@ -1,71 +0,0 @@
@@ -1,71 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
#include <nordic/nrf54l15_enga_cpuflpr.dtsi> |
||||
#include "nrf54l15pdk_nrf54l15-common.dtsi" |
||||
|
||||
/ { |
||||
model = "Nordic nRF54L15 PDK nRF54L15 FLPR MCU"; |
||||
compatible = "nordic,nrf54l15pdk_nrf54l15-cpuflpr"; |
||||
|
||||
chosen { |
||||
zephyr,console = &uart30; |
||||
zephyr,shell-uart = &uart30; |
||||
zephyr,code-partition = &cpuflpr_code_partition; |
||||
zephyr,flash = &cpuflpr_rram; |
||||
zephyr,sram = &cpuflpr_sram; |
||||
}; |
||||
}; |
||||
|
||||
&cpuflpr_sram { |
||||
status = "okay"; |
||||
/* size must be increased due to booting from SRAM */ |
||||
reg = <0x20028000 DT_SIZE_K(96)>; |
||||
ranges = <0x0 0x20028000 0x18000>; |
||||
}; |
||||
|
||||
&cpuflpr_rram { |
||||
partitions { |
||||
compatible = "fixed-partitions"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
|
||||
cpuflpr_code_partition: partition@0 { |
||||
label = "image-0"; |
||||
reg = <0x0 DT_SIZE_K(96)>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&grtc { |
||||
owned-channels = <3 4>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart30 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&gpio0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&gpio1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&gpio2 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&gpiote20 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&gpiote30 { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,18 +0,0 @@
@@ -1,18 +0,0 @@
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
identifier: nrf54l15pdk/nrf54l15/cpuflpr |
||||
name: nRF54L15-PDK-nRF54L15-Fast-Lightweight-Peripheral-Processor |
||||
type: mcu |
||||
arch: riscv |
||||
toolchain: |
||||
- zephyr |
||||
sysbuild: true |
||||
ram: 96 |
||||
flash: 96 |
||||
supported: |
||||
- counter |
||||
- gpio |
||||
- i2c |
||||
- spi |
||||
- watchdog |
||||
@ -1,7 +0,0 @@
@@ -1,7 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
#include "nrf54l15pdk_nrf54l15_common_0_2_1.dtsi" |
||||
@ -1,17 +0,0 @@
@@ -1,17 +0,0 @@
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
# Enable UART driver |
||||
CONFIG_SERIAL=y |
||||
|
||||
# Enable console |
||||
CONFIG_CONSOLE=y |
||||
CONFIG_UART_CONSOLE=y |
||||
|
||||
# Enable GPIO |
||||
CONFIG_GPIO=y |
||||
|
||||
CONFIG_USE_DT_CODE_PARTITION=y |
||||
|
||||
# Execute from SRAM |
||||
CONFIG_XIP=n |
||||
@ -1,12 +0,0 @@
@@ -1,12 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
#include "nrf54l15pdk_nrf54l15_cpuflpr.dts" |
||||
|
||||
&cpuflpr_sram { |
||||
reg = <0x2002f000 DT_SIZE_K(68)>; |
||||
ranges = <0x0 0x2002f000 0x11000>; |
||||
}; |
||||
@ -1,18 +0,0 @@
@@ -1,18 +0,0 @@
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
identifier: nrf54l15pdk/nrf54l15/cpuflpr/xip |
||||
name: nRF54L15-PDK-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP) |
||||
type: mcu |
||||
arch: riscv |
||||
toolchain: |
||||
- zephyr |
||||
sysbuild: true |
||||
ram: 68 |
||||
flash: 96 |
||||
supported: |
||||
- counter |
||||
- gpio |
||||
- i2c |
||||
- spi |
||||
- watchdog |
||||
@ -1,7 +0,0 @@
@@ -1,7 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
#include "nrf54l15pdk_nrf54l15_common_0_2_1.dtsi" |
||||
@ -1,15 +0,0 @@
@@ -1,15 +0,0 @@
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
# Enable UART driver |
||||
CONFIG_SERIAL=y |
||||
|
||||
# Enable console |
||||
CONFIG_CONSOLE=y |
||||
CONFIG_UART_CONSOLE=y |
||||
|
||||
# Enable GPIO |
||||
CONFIG_GPIO=y |
||||
|
||||
# Execute from RRAM |
||||
CONFIG_XIP=y |
||||
@ -1,12 +0,0 @@
@@ -1,12 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
&uart20 { |
||||
compatible = "nordic,nrf-uarte"; |
||||
current-speed = <1000000>; |
||||
status = "okay"; |
||||
hw-flow-control; |
||||
}; |
||||
@ -1,33 +0,0 @@
@@ -1,33 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
&uart20 { |
||||
compatible = "nordic,nrf-uarte"; |
||||
current-speed = <1000000>; |
||||
status = "okay"; |
||||
hw-flow-control; |
||||
}; |
||||
|
||||
&radio { |
||||
status = "okay"; |
||||
/* This is an example number of antennas that may be available |
||||
* on antenna matrix board. |
||||
*/ |
||||
dfe-antenna-num = <10>; |
||||
/* This is an example switch pattern that will be used to set an |
||||
* antenna for Tx PDU (period before start of Tx CTE). |
||||
*/ |
||||
dfe-pdu-antenna = <0x0>; |
||||
|
||||
/* These are example GPIO pin numbers that are provided to |
||||
* Radio peripheral. The pins will be acquired by Radio to |
||||
* drive antenna switching when AoD is enabled. |
||||
*/ |
||||
dfegpio0-gpios = <&gpio1 4 0>; |
||||
dfegpio1-gpios = <&gpio1 5 0>; |
||||
dfegpio2-gpios = <&gpio1 6 0>; |
||||
dfegpio3-gpios = <&gpio1 7 0>; |
||||
}; |
||||
@ -1,9 +0,0 @@
@@ -1,9 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
&mx25r64 { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,20 +0,0 @@
@@ -1,20 +0,0 @@
|
||||
/* |
||||
* Copyright 2024 Nordic Semiconductor ASA |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/ { |
||||
mbox-consumer { |
||||
compatible = "vnd,mbox-consumer"; |
||||
mboxes = <&cpuapp_vevif_rx 15>, <&cpuapp_vevif_tx 16>; |
||||
mbox-names = "rx", "tx"; |
||||
}; |
||||
}; |
||||
|
||||
&cpuapp_vevif_rx { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&cpuapp_vevif_tx { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,24 +0,0 @@
@@ -1,24 +0,0 @@
|
||||
/* |
||||
* Copyright 2024 Nordic Semiconductor ASA |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/ { |
||||
mbox-consumer { |
||||
compatible = "vnd,mbox-consumer"; |
||||
mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 15>; |
||||
mbox-names = "rx", "tx"; |
||||
}; |
||||
}; |
||||
|
||||
&cpuflpr_vevif_rx { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&cpuflpr_vevif_tx { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart30 { |
||||
/delete-property/ hw-flow-control; |
||||
}; |
||||
@ -1,24 +0,0 @@
@@ -1,24 +0,0 @@
|
||||
/* |
||||
* Copyright 2024 Nordic Semiconductor ASA |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/ { |
||||
mbox-consumer { |
||||
compatible = "vnd,mbox-consumer"; |
||||
mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 15>; |
||||
mbox-names = "rx", "tx"; |
||||
}; |
||||
}; |
||||
|
||||
&cpuflpr_vevif_rx { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&cpuflpr_vevif_tx { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart30 { |
||||
/delete-property/ hw-flow-control; |
||||
}; |
||||
@ -1,9 +0,0 @@
@@ -1,9 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
&mx25r64 { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,8 +0,0 @@
@@ -1,8 +0,0 @@
|
||||
/* |
||||
* Copyright 2024 Nordic Semiconductor ASA |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
&wdt31 { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,8 +0,0 @@
@@ -1,8 +0,0 @@
|
||||
/* |
||||
* Copyright 2024 Nordic Semiconductor ASA |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
&wdt31 { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,8 +0,0 @@
@@ -1,8 +0,0 @@
|
||||
/* |
||||
* Copyright 2024 Nordic Semiconductor ASA |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
&wdt31 { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,12 +0,0 @@
@@ -1,12 +0,0 @@
|
||||
# |
||||
# Copyright (c) 2024 Nordic Semiconductor ASA |
||||
# |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
# |
||||
|
||||
CONFIG_DISK_DRIVERS=y |
||||
CONFIG_DISK_DRIVER_FLASH=y |
||||
# There may be no files on internal SoC flash, so this Kconfig |
||||
# options has ben enabled to create some if listing does not |
||||
# find in the first place. |
||||
CONFIG_FS_SAMPLE_CREATE_SOME_ENTRIES=y |
||||
@ -1,45 +0,0 @@
@@ -1,45 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/* Because FAT FS needs at least 64kiB partition and default |
||||
* storage_partition is 36kiB for this board, we need to reorganize |
||||
* partitions to get at least 64KiB. |
||||
*/ |
||||
/delete-node/ &slot0_partition; |
||||
/delete-node/ &slot1_partition; |
||||
/delete-node/ &slot0_ns_partition; |
||||
/delete-node/ &slot1_ns_partition; |
||||
/delete-node/ &storage_partition; |
||||
|
||||
&cpuapp_rram { |
||||
partitions { |
||||
compatible = "fixed-partitions"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
|
||||
slot0_partition: parition@10000 { |
||||
reg = <0x00010000 DT_SIZE_K(300)>; |
||||
}; |
||||
slot1_partition: partition@5b000 { |
||||
reg = <0x0005b000 DT_SIZE_K(300)>; |
||||
}; |
||||
|
||||
storage_partition: partition@a6000 { |
||||
label = "storage"; |
||||
reg = <0x000a6000 DT_SIZE_K(128)>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
/ { |
||||
msc_disk0 { |
||||
status="okay"; |
||||
compatible = "zephyr,flash-disk"; |
||||
partition = <&storage_partition>; |
||||
disk-name = "SD"; |
||||
cache-size = <512>; |
||||
}; |
||||
}; |
||||
@ -1,41 +0,0 @@
@@ -1,41 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/ { |
||||
soc { |
||||
reserved-memory { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
|
||||
sram_rx: memory@20018000 { |
||||
reg = <0x20018000 0x0800>; |
||||
}; |
||||
|
||||
sram_tx: memory@20020000 { |
||||
reg = <0x20020000 0x0800>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
ipc { |
||||
ipc0: ipc0 { |
||||
compatible = "zephyr,ipc-icmsg"; |
||||
tx-region = <&sram_tx>; |
||||
rx-region = <&sram_rx>; |
||||
mboxes = <&cpuapp_vevif_rx 15>, <&cpuapp_vevif_tx 16>; |
||||
mbox-names = "rx", "tx"; |
||||
status = "okay"; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&cpuapp_vevif_rx { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&cpuapp_vevif_tx { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,45 +0,0 @@
@@ -1,45 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/ { |
||||
soc { |
||||
reserved-memory { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
|
||||
sram_tx: memory@20018000 { |
||||
reg = <0x20018000 0x0800>; |
||||
}; |
||||
|
||||
sram_rx: memory@20020000 { |
||||
reg = <0x20020000 0x0800>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
ipc { |
||||
ipc0: ipc0 { |
||||
compatible = "zephyr,ipc-icmsg"; |
||||
tx-region = <&sram_tx>; |
||||
rx-region = <&sram_rx>; |
||||
mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 15>; |
||||
mbox-names = "rx", "tx"; |
||||
status = "okay"; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&cpuflpr_vevif_rx { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&cpuflpr_vevif_tx { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart30 { |
||||
/delete-property/ hw-flow-control; |
||||
}; |
||||
@ -1,2 +0,0 @@
@@ -1,2 +0,0 @@
|
||||
CONFIG_NVS=y |
||||
CONFIG_SETTINGS_NVS=y |
||||
@ -1 +0,0 @@
@@ -1 +0,0 @@
|
||||
SB_CONFIG_REMOTE_BOARD="nrf54l15pdk/nrf54l15/cpuflpr" |
||||
@ -1,29 +0,0 @@
@@ -1,29 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/ { |
||||
soc { |
||||
reserved-memory { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
cpuflpr_code_partition: image@165000 { |
||||
/* FLPR core code partition */ |
||||
reg = <0x165000 DT_SIZE_K(96)>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&uart30 { |
||||
status = "reserved"; |
||||
}; |
||||
|
||||
&cpuflpr_vpr { |
||||
execution-memory = <&cpuflpr_code_partition>; |
||||
}; |
||||
|
||||
&cpuapp_vevif_tx { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,43 +0,0 @@
@@ -1,43 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/ { |
||||
soc { |
||||
reserved-memory { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
cpuflpr_code_partition: image@165000 { |
||||
/* FLPR core code partition */ |
||||
reg = <0x165000 DT_SIZE_K(96)>; |
||||
}; |
||||
}; |
||||
|
||||
cpuflpr_sram_code_data: memory@20028000 { |
||||
compatible = "mmio-sram"; |
||||
reg = <0x20028000 DT_SIZE_K(96)>; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
ranges = <0x0 0x20028000 0x18000>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&uart30 { |
||||
status = "reserved"; |
||||
}; |
||||
|
||||
&cpuapp_sram { |
||||
reg = <0x20000000 DT_SIZE_K(160)>; |
||||
ranges = <0x0 0x20000000 0x28000>; |
||||
}; |
||||
|
||||
&cpuflpr_vpr { |
||||
execution-memory = <&cpuflpr_sram_code_data>; |
||||
source-memory = <&cpuflpr_code_partition>; |
||||
}; |
||||
|
||||
&cpuapp_vevif_tx { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,43 +0,0 @@
@@ -1,43 +0,0 @@
|
||||
/* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
*/ |
||||
|
||||
/ { |
||||
zephyr,user { |
||||
io-channels = <&adc 0>, <&adc 1> , <&adc 2>; |
||||
}; |
||||
}; |
||||
|
||||
&adc { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
channel@0 { |
||||
reg = <0>; |
||||
zephyr,gain = "ADC_GAIN_1"; |
||||
zephyr,reference = "ADC_REF_INTERNAL"; |
||||
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>; |
||||
zephyr,input-positive = <NRF_SAADC_AIN1>; |
||||
zephyr,resolution = <10>; |
||||
}; |
||||
|
||||
channel@1 { |
||||
reg = <1>; |
||||
zephyr,gain = "ADC_GAIN_1_4"; |
||||
zephyr,reference = "ADC_REF_EXTERNAL0"; |
||||
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>; |
||||
zephyr,input-positive = <NRF_SAADC_AIN4>; |
||||
zephyr,resolution = <12>; |
||||
}; |
||||
|
||||
channel@2 { |
||||
reg = <2>; |
||||
zephyr,gain = "ADC_GAIN_2_5"; |
||||
zephyr,reference = "ADC_REF_INTERNAL"; |
||||
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>; |
||||
zephyr,input-positive = <NRF_SAADC_AIN2>; |
||||
zephyr,resolution = <10>; |
||||
}; |
||||
}; |
||||
@ -1,21 +0,0 @@
@@ -1,21 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/ { |
||||
resources { |
||||
compatible = "test-gpio-basic-api"; |
||||
out-gpios = <&gpio1 10 0>; |
||||
in-gpios = <&gpio1 11 0>; |
||||
}; |
||||
}; |
||||
|
||||
&gpiote20 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&gpio1 { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,21 +0,0 @@
@@ -1,21 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/ { |
||||
resources { |
||||
compatible = "test-gpio-basic-api"; |
||||
out-gpios = <&gpio1 10 0>; |
||||
in-gpios = <&gpio1 11 0>; |
||||
}; |
||||
}; |
||||
|
||||
&gpiote20 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&gpio1 { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,21 +0,0 @@
@@ -1,21 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/ { |
||||
resources { |
||||
compatible = "test-gpio-basic-api"; |
||||
out-gpios = <&gpio1 10 0>; |
||||
in-gpios = <&gpio1 11 0>; |
||||
}; |
||||
}; |
||||
|
||||
&gpiote20 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&gpio1 { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,30 +0,0 @@
@@ -1,30 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/* i2s-node0 is the transmitter/receiver */ |
||||
|
||||
/ { |
||||
aliases { |
||||
i2s-node0 = &i2s20; |
||||
}; |
||||
}; |
||||
|
||||
&pinctrl { |
||||
i2s20_default_alt: i2s20_default_alt { |
||||
group1 { |
||||
psels = <NRF_PSEL(I2S_SCK_M, 1, 11)>, |
||||
<NRF_PSEL(I2S_LRCK_M, 1, 12)>, |
||||
<NRF_PSEL(I2S_SDOUT, 1, 8)>, |
||||
<NRF_PSEL(I2S_SDIN, 1, 9)>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&i2s20 { |
||||
status = "okay"; |
||||
pinctrl-0 = <&i2s20_default_alt>; |
||||
pinctrl-names = "default"; |
||||
}; |
||||
@ -1,30 +0,0 @@
@@ -1,30 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/* i2s-node0 is the transmitter/receiver */ |
||||
|
||||
/ { |
||||
aliases { |
||||
i2s-node0 = &i2s20; |
||||
}; |
||||
}; |
||||
|
||||
&pinctrl { |
||||
i2s20_default_alt: i2s20_default_alt { |
||||
group1 { |
||||
psels = <NRF_PSEL(I2S_SCK_M, 1, 11)>, |
||||
<NRF_PSEL(I2S_LRCK_M, 1, 12)>, |
||||
<NRF_PSEL(I2S_SDOUT, 1, 8)>, |
||||
<NRF_PSEL(I2S_SDIN, 1, 9)>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&i2s20 { |
||||
status = "okay"; |
||||
pinctrl-0 = <&i2s20_default_alt>; |
||||
pinctrl-names = "default"; |
||||
}; |
||||
@ -1,23 +0,0 @@
@@ -1,23 +0,0 @@
|
||||
/* |
||||
* Copyright 2024 Nordic Semiconductor ASA |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/ { |
||||
mbox-consumer { |
||||
compatible = "vnd,mbox-consumer"; |
||||
mboxes = <&cpuapp_vevif_tx 16>, <&cpuapp_vevif_tx 32>, |
||||
<&cpuapp_vevif_rx 15>, <&cpuapp_vevif_rx 32>; |
||||
mbox-names = "remote_valid", "remote_incorrect", |
||||
"local_valid", "local_incorrect"; |
||||
|
||||
}; |
||||
}; |
||||
|
||||
&cpuapp_vevif_rx { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&cpuapp_vevif_tx { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,20 +0,0 @@
@@ -1,20 +0,0 @@
|
||||
&pinctrl { |
||||
pwm_default: pwm_default { |
||||
group1 { |
||||
psels = <NRF_PSEL(PWM_OUT0, 1, 8)>; |
||||
}; |
||||
}; |
||||
pwm_sleep: pwm_sleep { |
||||
group1 { |
||||
psels = <NRF_PSEL(PWM_OUT0, 1, 8)>; |
||||
low-power-enable; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&pwm20 { |
||||
status = "okay"; |
||||
pinctrl-0 = <&pwm_default>; |
||||
pinctrl-1 = <&pwm_sleep>; |
||||
pinctrl-names = "default", "sleep"; |
||||
}; |
||||
@ -1,3 +0,0 @@
@@ -1,3 +0,0 @@
|
||||
temp_sensor: &temp { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,36 +0,0 @@
@@ -1,36 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
&pinctrl { |
||||
uart21_default: uart21_default { |
||||
group1 { |
||||
psels = <NRF_PSEL(UART_TX, 1, 10)>, |
||||
<NRF_PSEL(UART_RX, 1, 11)>; |
||||
}; |
||||
}; |
||||
|
||||
uart21_sleep: uart21_sleep { |
||||
group1 { |
||||
psels = <NRF_PSEL(UART_TX, 1, 10)>, |
||||
<NRF_PSEL(UART_RX, 1, 11)>; |
||||
low-power-enable; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
/ { |
||||
chosen { |
||||
zephyr,console = &uart20; |
||||
}; |
||||
}; |
||||
|
||||
dut: &uart21 { |
||||
status = "okay"; |
||||
current-speed = <115200>; |
||||
pinctrl-0 = <&uart21_default>; |
||||
pinctrl-1 = <&uart21_sleep>; |
||||
pinctrl-names = "default", "sleep"; |
||||
}; |
||||
@ -1,30 +0,0 @@
@@ -1,30 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
&pinctrl { |
||||
uart21_default: uart21_default { |
||||
group1 { |
||||
psels = <NRF_PSEL(UART_TX, 1, 10)>, |
||||
<NRF_PSEL(UART_RX, 1, 11)>; |
||||
}; |
||||
}; |
||||
|
||||
uart21_sleep: uart21_sleep { |
||||
group1 { |
||||
psels = <NRF_PSEL(UART_TX, 1, 10)>, |
||||
<NRF_PSEL(UART_RX, 1, 11)>; |
||||
low-power-enable; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
dut: &uart21 { |
||||
status = "okay"; |
||||
current-speed = <115200>; |
||||
pinctrl-0 = <&uart21_default>; |
||||
pinctrl-1 = <&uart21_sleep>; |
||||
pinctrl-names = "default", "sleep"; |
||||
}; |
||||
@ -1,54 +0,0 @@
@@ -1,54 +0,0 @@
|
||||
/* SPDX-License-Identifier: Apache-2.0 */ |
||||
|
||||
&pinctrl { |
||||
uart21_default: uart21_default { |
||||
group1 { |
||||
psels = <NRF_PSEL(UART_RX, 1, 8)>, |
||||
<NRF_PSEL(UART_RTS, 1, 10)>; |
||||
}; |
||||
}; |
||||
|
||||
uart21_sleep: uart21_sleep { |
||||
group1 { |
||||
psels = <NRF_PSEL(UART_RX, 1, 8)>, |
||||
<NRF_PSEL(UART_RTS, 1, 10)>; |
||||
low-power-enable; |
||||
}; |
||||
}; |
||||
|
||||
uart22_default: uart22_default { |
||||
group1 { |
||||
psels = |
||||
<NRF_PSEL(UART_CTS, 1, 11)>; |
||||
bias-pull-up; |
||||
}; |
||||
group2 { |
||||
psels = <NRF_PSEL(UART_TX, 1, 9)>; |
||||
}; |
||||
}; |
||||
|
||||
uart22_sleep: uart22_sleep { |
||||
group1 { |
||||
psels = <NRF_PSEL(UART_TX, 1, 9)>, |
||||
<NRF_PSEL(UART_CTS, 1, 11)>; |
||||
low-power-enable; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
dut: &uart21 { |
||||
status = "okay"; |
||||
current-speed = <115200>; |
||||
pinctrl-0 = <&uart21_default>; |
||||
pinctrl-1 = <&uart21_sleep>; |
||||
pinctrl-names = "default", "sleep"; |
||||
}; |
||||
|
||||
dut_aux: &uart22 { |
||||
status = "okay"; |
||||
current-speed = <115200>; |
||||
pinctrl-0 = <&uart22_default>; |
||||
pinctrl-1 = <&uart22_sleep>; |
||||
pinctrl-names = "default", "sleep"; |
||||
disable-rx; |
||||
}; |
||||
@ -1,22 +0,0 @@
@@ -1,22 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2024 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/delete-node/ &slot0_ns_partition; |
||||
/delete-node/ &slot1_partition; |
||||
/delete-node/ &slot1_ns_partition; |
||||
|
||||
&cpuapp_rram { |
||||
partitions { |
||||
compatible = "fixed-partitions"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
|
||||
small_partition: partition@67000 { |
||||
label = "small"; |
||||
reg = <0x00067000 0x00010000>; |
||||
}; |
||||
}; |
||||
}; |
||||
Loading…
Reference in new issue