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/*
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* Copyright (c) 2025 Silicon Laboratories Inc. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <errno.h> |
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#include <zephyr/irq.h> |
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#include <zephyr/types.h> |
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#include <zephyr/device.h> |
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#include <zephyr/sys/util.h> |
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#include <zephyr/sys/bitarray.h> |
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#include <zephyr/drivers/watchdog.h> |
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#include <zephyr/drivers/clock_control.h> |
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#include <math.h> |
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#include "rsi_wwdt.h" |
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#include "rsi_sysrtc.h" |
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#define DT_DRV_COMPAT silabs_siwx91x_wdt |
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#define SIWX91X_WDT_SYSTEM_RESET_TIMER_MASK 0x0000001F |
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struct siwx91x_wdt_config { |
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/* WDT register base address */ |
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MCU_WDT_Type *reg; |
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/* Pointer to the clock device structure */ |
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const struct device *clock_dev; |
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/* Clock control subsystem */ |
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clock_control_subsys_t clock_subsys; |
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/* Function pointer for the IRQ (Interrupt Request) configuration */ |
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void (*irq_config)(void); |
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}; |
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struct siwx91x_wdt_data { |
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/* Callback function to be called on watchdog timer events */ |
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wdt_callback_t callback; |
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/* WDT operating clock (LF-FSM) frequency */ |
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uint32_t clock_frequency; |
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/* Timer system reset duration in ms */ |
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uint8_t delay_reset; |
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/* Timer interrupt duration in ms */ |
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uint8_t delay_irq; |
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/* Flag indicating the timeout install status */ |
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bool timeout_install_status; |
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/* Flag indicating the setup status */ |
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bool setup_status; |
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}; |
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/* Function to get the delay in milliseconds from the register value */ |
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static uint32_t siwx91x_wdt_delay_from_hw(uint8_t value, int clock_frequency) |
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{ |
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uint32_t ticks = BIT(value); |
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float timeout = (float)ticks / clock_frequency; |
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timeout *= 1000; |
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/* Return the timeout value as an unsigned 32-bit integer in milliseconds */ |
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return (uint32_t)timeout; |
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} |
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/* Function to get the register value from the delay in milliseconds */ |
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static uint8_t siwx91x_wdt_delay_to_hw(uint32_t delay, int clock_frequency) |
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{ |
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/* reg_value = log((timeout * clock_frequency)/1000)base2 */ |
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float value = ((float)delay * (float)clock_frequency) / 1000; |
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float result = log2f(value); |
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/* Round the result to nearest integer */ |
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result = roundf(result); |
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return (uint8_t)result; |
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} |
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static int siwx91x_wdt_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg) |
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{ |
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struct siwx91x_wdt_data *data = dev->data; |
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/* Check the WDT setup status */ |
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if (data->setup_status) { |
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/* WDT setup is already done */ |
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return -EBUSY; |
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} |
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/* Check the WDT timeout status */ |
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if (data->timeout_install_status) { |
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/* Only single timeout can be installed */ |
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return -ENOMEM; |
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} |
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if (cfg->window.max > siwx91x_wdt_delay_from_hw(SIWX91X_WDT_SYSTEM_RESET_TIMER_MASK, |
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data->clock_frequency) || |
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cfg->window.max == 0) { |
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/* Requested value is out of range */ |
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return -EINVAL; |
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} |
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if (cfg->window.min > 0) { |
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/* This feature is currently not supported */ |
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return -ENOTSUP; |
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} |
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switch (cfg->flags) { |
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case WDT_FLAG_RESET_SOC: |
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case WDT_FLAG_RESET_CPU_CORE: |
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if (cfg->callback != NULL) { |
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/* Callback is not supported for reset flags */ |
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return -ENOTSUP; |
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} |
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data->delay_reset = siwx91x_wdt_delay_to_hw(cfg->window.max, data->clock_frequency); |
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/* During a system or CPU core reset, interrupts are not needed. Thus, we set
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* the interrupt time to 0 to ensure no interrupts occur while resetting. |
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*/ |
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data->delay_irq = 0; |
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/* Mask the WWDT interrupt */ |
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RSI_WWDT_IntrMask(); |
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break; |
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case WDT_FLAG_RESET_NONE: |
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/* Set the reset time to maximum value */ |
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data->delay_reset = SIWX91X_WDT_SYSTEM_RESET_TIMER_MASK; |
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data->delay_irq = siwx91x_wdt_delay_to_hw(cfg->window.max, data->clock_frequency); |
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if (cfg->callback != NULL) { |
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data->callback = cfg->callback; |
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} |
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break; |
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default: |
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/* Unsupported WDT config options */ |
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return -ENOTSUP; |
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} |
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data->timeout_install_status = true; |
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return 0; |
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} |
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/* Function to setup and start WDT */ |
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static int siwx91x_wdt_setup(const struct device *dev, uint8_t options) |
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{ |
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const struct siwx91x_wdt_config *config = dev->config; |
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struct siwx91x_wdt_data *data = dev->data; |
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/* Check the WDT setup status */ |
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if (data->setup_status) { |
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/* WDT is already running */ |
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return -EBUSY; |
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} |
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/* Check the WDT timeout status */ |
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if (!data->timeout_install_status) { |
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/* Timeout need to be set before setup */ |
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return -ENOTSUP; |
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} |
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if (options & (WDT_OPT_PAUSE_IN_SLEEP)) { |
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return -ENOTSUP; |
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} |
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RSI_WWDT_ConfigSysRstTimer(config->reg, data->delay_reset); |
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RSI_WWDT_ConfigIntrTimer(config->reg, data->delay_irq); |
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RSI_WWDT_Start(config->reg); |
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data->setup_status = true; |
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return 0; |
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} |
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static int siwx91x_wdt_disable(const struct device *dev) |
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{ |
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const struct siwx91x_wdt_config *config = dev->config; |
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struct siwx91x_wdt_data *data = dev->data; |
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if (!data->timeout_install_status) { |
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/* No timeout installed */ |
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return -EFAULT; |
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} |
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RSI_WWDT_Disable(config->reg); |
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data->timeout_install_status = false; |
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data->setup_status = false; |
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return 0; |
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} |
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static int siwx91x_wdt_feed(const struct device *dev, int channel_id) |
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{ |
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const struct siwx91x_wdt_config *config = dev->config; |
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struct siwx91x_wdt_data *data = dev->data; |
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if (!(data->timeout_install_status && data->setup_status)) { |
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/* WDT is not configured */ |
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return -EINVAL; |
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} |
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if (channel_id != 0) { |
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/* Channel id must be 0 */ |
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return -EINVAL; |
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} |
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RSI_WWDT_ReStart(config->reg); |
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return 0; |
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} |
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static void siwx91x_wdt_isr(const struct device *dev) |
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{ |
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const struct siwx91x_wdt_config *config = dev->config; |
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struct siwx91x_wdt_data *data = dev->data; |
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/* Clear WDT interrupt */ |
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RSI_WWDT_IntrClear(); |
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if (data->delay_irq) { |
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/* Restart the timer */ |
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RSI_WWDT_ReStart(config->reg); |
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} |
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if (data->callback != NULL) { |
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data->callback(dev, 0); |
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} |
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} |
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static int siwx91x_wdt_init(const struct device *dev) |
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{ |
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const struct siwx91x_wdt_config *config = dev->config; |
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struct siwx91x_wdt_data *data = dev->data; |
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int ret; |
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ret = clock_control_on(config->clock_dev, config->clock_subsys); |
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if (ret) { |
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return ret; |
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} |
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ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, |
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&data->clock_frequency); |
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if (ret) { |
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return ret; |
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} |
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RSI_WWDT_Init(config->reg); |
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config->irq_config(); |
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RSI_WWDT_IntrUnMask(); |
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return 0; |
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} |
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static DEVICE_API(wdt, siwx91x_wdt_driver_api) = { |
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.setup = siwx91x_wdt_setup, |
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.disable = siwx91x_wdt_disable, |
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.install_timeout = siwx91x_wdt_install_timeout, |
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.feed = siwx91x_wdt_feed, |
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}; |
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#define siwx91x_WDT_INIT(inst) \ |
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static struct siwx91x_wdt_data siwx91x_wdt_data_##inst; \ |
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static void siwx91x_wdt_irq_configure_##inst(void) \ |
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{ \ |
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IRQ_CONNECT(DT_INST_IRQ(inst, irq), DT_INST_IRQ(inst, priority), siwx91x_wdt_isr, \ |
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DEVICE_DT_INST_GET(inst), 0); \ |
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irq_enable(DT_INST_IRQ(inst, irq)); \ |
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} \ |
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static const struct siwx91x_wdt_config siwx91x_wdt_config_##inst = { \ |
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.reg = (MCU_WDT_Type *)DT_INST_REG_ADDR(inst), \ |
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \ |
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.clock_subsys = (clock_control_subsys_t)DT_INST_PHA(inst, clocks, clkid), \ |
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.irq_config = siwx91x_wdt_irq_configure_##inst, \ |
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}; \ |
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DEVICE_DT_INST_DEFINE(inst, &siwx91x_wdt_init, NULL, &siwx91x_wdt_data_##inst, \ |
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&siwx91x_wdt_config_##inst, PRE_KERNEL_1, \ |
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &siwx91x_wdt_driver_api); |
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DT_INST_FOREACH_STATUS_OKAY(siwx91x_WDT_INIT) |
Sai Santhosh Malae
5 months ago
committed by
Benjamin Cabé