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@ -536,7 +536,7 @@ static int andes_cache_init(void) |
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cache_cfg.instr_line_size = CONFIG_ICACHE_LINE_SIZE; |
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cache_cfg.instr_line_size = CONFIG_ICACHE_LINE_SIZE; |
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#elif DT_NODE_HAS_PROP(DT_PATH(cpus, cpu_0), i_cache_line_size) |
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#elif DT_NODE_HAS_PROP(DT_PATH(cpus, cpu_0), i_cache_line_size) |
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cache_cfg.instr_line_size = |
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cache_cfg.instr_line_size = |
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DT_PROP(DT_PATH(cpus, cpu_0), "i_cache_line_size"); |
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DT_PROP(DT_PATH(cpus, cpu_0), i_cache_line_size); |
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#else |
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#else |
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LOG_ERR("Please specific the i-cache-line-size " |
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LOG_ERR("Please specific the i-cache-line-size " |
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"CPU0 property of the DT"); |
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"CPU0 property of the DT"); |
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@ -560,7 +560,7 @@ static int andes_cache_init(void) |
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cache_cfg.data_line_size = CONFIG_DCACHE_LINE_SIZE; |
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cache_cfg.data_line_size = CONFIG_DCACHE_LINE_SIZE; |
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#elif DT_NODE_HAS_PROP(DT_PATH(cpus, cpu_0), d_cache_line_size) |
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#elif DT_NODE_HAS_PROP(DT_PATH(cpus, cpu_0), d_cache_line_size) |
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cache_cfg.data_line_size = |
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cache_cfg.data_line_size = |
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DT_PROP(DT_PATH(cpus, cpu_0), "d_cache_line_size"); |
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DT_PROP(DT_PATH(cpus, cpu_0), d_cache_line_size); |
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#else |
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#else |
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LOG_ERR("Please specific the d-cache-line-size " |
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LOG_ERR("Please specific the d-cache-line-size " |
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"CPU0 property of the DT"); |
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"CPU0 property of the DT"); |
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