diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml
index 60b258ad5a1..7055f3cf467 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022-2024 NXP
+# Copyright 2022-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: s32z2xxdc2/s32z270/rtu0
@@ -20,4 +20,5 @@ supported:
   - i2c
   - dma
   - pwm
+  - sent
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml
index c35cc47699b..ec8257e4269 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml
@@ -1,4 +1,4 @@
-# Copyright 2023-2024 NXP
+# Copyright 2023-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: s32z2xxdc2@D/s32z270/rtu0
@@ -20,4 +20,5 @@ supported:
   - i2c
   - dma
   - pwm
+  - sent
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml
index 3d4f2062cc9..8ba76583d98 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022-2024 NXP
+# Copyright 2022-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: s32z2xxdc2/s32z270/rtu1
@@ -20,4 +20,5 @@ supported:
   - i2c
   - dma
   - pwm
+  - sent
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml
index 334d75319ca..cfbbae95ae8 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022-2024 NXP
+# Copyright 2022-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: s32z2xxdc2@D/s32z270/rtu1
@@ -20,4 +20,5 @@ supported:
   - i2c
   - dma
   - pwm
+  - sent
 vendor: nxp
diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi
index 0c976a30418..e5221aa9f1d 100644
--- a/dts/arm/nxp/nxp_s32z27x_r52.dtsi
+++ b/dts/arm/nxp/nxp_s32z27x_r52.dtsi
@@ -1465,5 +1465,111 @@
 			#size-cells = <0>;
 			status = "disabled";
 		};
+
+		sent0: sent@40a50000 {
+			compatible = "nxp,s32-sent";
+			reg = <0x40a50000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 429 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 430 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "fast_msg", "serial_msg", "error";
+			clocks = <&clock NXP_S32_P1_REG_INTF_CLK>;
+			status = "disabled";
+
+			sent0_ch0: ch@0 {
+				reg = <0>;
+				status = "disabled";
+			};
+
+			sent0_ch1: ch@1 {
+				reg = <1>;
+				status = "disabled";
+			};
+
+			sent0_ch2: ch@2 {
+				reg = <2>;
+				status = "disabled";
+			};
+
+			sent0_ch3: ch@3 {
+				reg = <3>;
+				status = "disabled";
+			};
+
+			sent0_ch4: ch@4 {
+				reg = <4>;
+				status = "disabled";
+			};
+
+			sent0_ch5: ch@5 {
+				reg = <5>;
+				status = "disabled";
+			};
+
+			sent0_ch6: ch@6 {
+				reg = <6>;
+				status = "disabled";
+			};
+
+			sent0_ch7: ch@7 {
+				reg = <7>;
+				status = "disabled";
+			};
+		};
+
+		sent1: sent@42050000 {
+			compatible = "nxp,s32-sent";
+			reg = <0x42050000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 456 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 457 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "fast_msg", "serial_msg", "error";
+			clocks = <&clock NXP_S32_P4_REG_INTF_CLK>;
+			status = "disabled";
+
+			sent1_ch0: ch@0 {
+				reg = <0>;
+				status = "disabled";
+			};
+
+			sent1_ch1: ch@1 {
+				reg = <1>;
+				status = "disabled";
+			};
+
+			sent1_ch2: ch@2 {
+				reg = <2>;
+				status = "disabled";
+			};
+
+			sent1_ch3: ch@3 {
+				reg = <3>;
+				status = "disabled";
+			};
+
+			sent1_ch4: ch@4 {
+				reg = <4>;
+				status = "disabled";
+			};
+
+			sent1_ch5: ch@5 {
+				reg = <5>;
+				status = "disabled";
+			};
+
+			sent1_ch6: ch@6 {
+				reg = <6>;
+				status = "disabled";
+			};
+
+			sent1_ch7: ch@7 {
+				reg = <7>;
+				status = "disabled";
+			};
+		};
 	};
 };