@ -21,215 +21,215 @@
@@ -21,215 +21,215 @@
* Starts at offset 0x100 .
*/
struct __pdc {
uint 32_trpr ; /* 0x100 Receive Pointer */
uint 32_trcr ; /* 0x104 Receive Counter */
uint 32_ttpr ; /* 0x108 Transmit Pointer */
uint 32_ttcr ; /* 0x10C Transmit Counter */
uint 32_trnpr ; /* 0x110 Receive Next Pointer */
uint 32_trncr ; /* 0x114 Receive Next Counter */
uint 32_ttnpr ; /* 0x118 Transmit Next Pointer */
uint 32_ttncr ; /* 0x11C Transmit Next Counter */
uint 32_tptcr ; /* 0x120 Transfer Control */
uint 32_tptsr ; /* 0x124 Transfer Status */
u 32_trpr ; /* 0x100 Receive Pointer */
u 32_trcr ; /* 0x104 Receive Counter */
u 32_ttpr ; /* 0x108 Transmit Pointer */
u 32_ttcr ; /* 0x10C Transmit Counter */
u 32_trnpr ; /* 0x110 Receive Next Pointer */
u 32_trncr ; /* 0x114 Receive Next Counter */
u 32_ttnpr ; /* 0x118 Transmit Next Pointer */
u 32_ttncr ; /* 0x11C Transmit Next Counter */
u 32_tptcr ; /* 0x120 Transfer Control */
u 32_tptsr ; /* 0x124 Transfer Status */
} ;
/* Enhanced Embedded Flash Controller */
struct __eefc {
uint 32_tfmr ; /* 0x00 Flash Mode Register */
uint 32_tfcr ; /* 0x04 Flash Command Register */
uint 32_tfsr ; /* 0x08 Flash Status Register */
uint 32_tfrr ; /* 0x0C Flash Result Register */
u 32_tfmr ; /* 0x00 Flash Mode Register */
u 32_tfcr ; /* 0x04 Flash Command Register */
u 32_tfsr ; /* 0x08 Flash Status Register */
u 32_tfrr ; /* 0x0C Flash Result Register */
} ;
/* PIO Controller */
struct __pio {
uint 32_tper ; /* 0x00 Enable */
uint 32_tpdr ; /* 0x04 Disable */
uint 32_tpsr ; /* 0x08 Status */
u 32_tper ; /* 0x00 Enable */
u 32_tpdr ; /* 0x04 Disable */
u 32_tpsr ; /* 0x08 Status */
uint 32_tres0 ; /* 0x0C reserved */
u 32_tres0 ; /* 0x0C reserved */
uint 32_toer ; /* 0x10 Output Enable */
uint 32_todr ; /* 0x14 Output Disable */
uint 32_tosr ; /* 0x18 Output Status */
u 32_toer ; /* 0x10 Output Enable */
u 32_todr ; /* 0x14 Output Disable */
u 32_tosr ; /* 0x18 Output Status */
uint 32_tres1 ; /* 0x1C reserved */
u 32_tres1 ; /* 0x1C reserved */
uint 32_tifer ; /* 0x20 Glitch Input Filter Enable */
uint 32_tifdr ; /* 0x24 Glitch Input Filter Disable */
uint 32_tifsr ; /* 0x28 Glitch Input Fitler Status */
u 32_tifer ; /* 0x20 Glitch Input Filter Enable */
u 32_tifdr ; /* 0x24 Glitch Input Filter Disable */
u 32_tifsr ; /* 0x28 Glitch Input Fitler Status */
uint 32_tres2 ; /* 0x2C reserved */
u 32_tres2 ; /* 0x2C reserved */
uint 32_tsodr ; /* 0x30 Set Output Data */
uint 32_tcodr ; /* 0x34 Clear Output Data */
uint 32_todsr ; /* 0x38 Output Data Status */
uint 32_tpdsr ; /* 0x3C Pin Data Status */
u 32_tsodr ; /* 0x30 Set Output Data */
u 32_tcodr ; /* 0x34 Clear Output Data */
u 32_todsr ; /* 0x38 Output Data Status */
u 32_tpdsr ; /* 0x3C Pin Data Status */
uint 32_tier ; /* 0x40 Interrupt Enable */
uint 32_tidr ; /* 0x44 Interrupt Disable */
uint 32_timr ; /* 0x48 Interrupt Mask */
uint 32_tisr ; /* 0x4C Interrupt Status */
u 32_tier ; /* 0x40 Interrupt Enable */
u 32_tidr ; /* 0x44 Interrupt Disable */
u 32_timr ; /* 0x48 Interrupt Mask */
u 32_tisr ; /* 0x4C Interrupt Status */
uint 32_tmder ; /* 0x50 Multi-driver Enable */
uint 32_tmddr ; /* 0x54 Multi-driver Disable */
uint 32_tmdsr ; /* 0x58 Multi-driver Status */
u 32_tmder ; /* 0x50 Multi-driver Enable */
u 32_tmddr ; /* 0x54 Multi-driver Disable */
u 32_tmdsr ; /* 0x58 Multi-driver Status */
uint 32_tres3 ; /* 0x5C reserved */
u 32_tres3 ; /* 0x5C reserved */
uint 32_tpudr ; /* 0x60 Pull-up Disable */
uint 32_tpuer ; /* 0x64 Pull-up Enable */
uint 32_tpusr ; /* 0x68 Pad Pull-up Status */
u 32_tpudr ; /* 0x60 Pull-up Disable */
u 32_tpuer ; /* 0x64 Pull-up Enable */
u 32_tpusr ; /* 0x68 Pad Pull-up Status */
uint 32_tres4 ; /* 0x6C reserved */
u 32_tres4 ; /* 0x6C reserved */
uint 32_tabsr ; /* 0x70 Peripheral AB Select */
u 32_tabsr ; /* 0x70 Peripheral AB Select */
uint 32_tres5 [ 3 ] ; /* 0x74-0x7C reserved */
u 32_tres5 [ 3 ] ; /* 0x74-0x7C reserved */
uint 32_tscifsr ; /* 0x80 System Clock Glitch Input */
u 32_tscifsr ; /* 0x80 System Clock Glitch Input */
/* Filter Select */
uint 32_tdifsr ; /* 0x84 Debouncing Input Filter */
u 32_tdifsr ; /* 0x84 Debouncing Input Filter */
/* Select */
uint 32_tifdgsr ; /* 0x88 Glitch or Debouncing Input */
u 32_tifdgsr ; /* 0x88 Glitch or Debouncing Input */
/* Filter Clock Selection */
/* Status */
uint 32_tscdr ; /* 0x8C Slow Clock Divider Debounce */
u 32_tscdr ; /* 0x8C Slow Clock Divider Debounce */
uint 32_tres6 [ 4 ] ; /* 0x90-0x9C reserved */
u 32_tres6 [ 4 ] ; /* 0x90-0x9C reserved */
uint 32_tower ; /* 0xA0 Output Write Enable */
uint 32_towdr ; /* 0xA4 Output Write Disable */
uint 32_towsr ; /* 0xA8 Output Write Status */
u 32_tower ; /* 0xA0 Output Write Enable */
u 32_towdr ; /* 0xA4 Output Write Disable */
u 32_towsr ; /* 0xA8 Output Write Status */
uint 32_tres7 ; /* 0xAC reserved */
u 32_tres7 ; /* 0xAC reserved */
uint 32_taimer ; /* 0xB0 Additional Interrupt Modes */
u 32_taimer ; /* 0xB0 Additional Interrupt Modes */
/* Enable */
uint 32_taimdr ; /* 0xB4 Additional Interrupt Modes */
u 32_taimdr ; /* 0xB4 Additional Interrupt Modes */
/* Disable */
uint 32_taimmr ; /* 0xB8 Additional Interrupt Modes */
u 32_taimmr ; /* 0xB8 Additional Interrupt Modes */
/* Mask */
uint 32_tres8 ; /* 0xBC reserved */
u 32_tres8 ; /* 0xBC reserved */
uint 32_tesr ; /* 0xC0 Edge Select */
uint 32_tlsr ; /* 0xC4 Level Select */
uint 32_telsr ; /* 0xC8 Edge/Level Status */
u 32_tesr ; /* 0xC0 Edge Select */
u 32_tlsr ; /* 0xC4 Level Select */
u 32_telsr ; /* 0xC8 Edge/Level Status */
uint 32_tres9 ; /* 0xCC reserved */
u 32_tres9 ; /* 0xCC reserved */
uint 32_tfellsr ; /* 0xD0 Falling Edge/Low Level Sel */
uint 32_trehlsr ; /* 0xD4 Rising Edge/High Level Sel */
uint 32_tfrlhsr ; /* 0xD8 Fall/Rise - Low/High Status */
u 32_tfellsr ; /* 0xD0 Falling Edge/Low Level Sel */
u 32_trehlsr ; /* 0xD4 Rising Edge/High Level Sel */
u 32_tfrlhsr ; /* 0xD8 Fall/Rise - Low/High Status */
uint 32_tres10 ; /* 0xDC reserved */
u 32_tres10 ; /* 0xDC reserved */
uint 32_tlocksr ; /* 0xE0 Lock Status */
u 32_tlocksr ; /* 0xE0 Lock Status */
uint 32_twpmr ; /* 0xE4 Write Protect Mode */
uint 32_twpsr ; /* 0xE8 Write Protect Status */
u 32_twpmr ; /* 0xE4 Write Protect Mode */
u 32_twpsr ; /* 0xE8 Write Protect Status */
} ;
/* Power Management Controller */
struct __pmc {
uint 32_tscer ; /* 0x00 System Clock Enable */
uint 32_tscdr ; /* 0x04 System Clock Disable */
uint 32_tscsr ; /* 0x08 System Clock Status */
u 32_tscer ; /* 0x00 System Clock Enable */
u 32_tscdr ; /* 0x04 System Clock Disable */
u 32_tscsr ; /* 0x08 System Clock Status */
uint 32_tres0 ; /* 0x0C reserved */
u 32_tres0 ; /* 0x0C reserved */
uint 32_tpcer0 ; /* 0x10 Peripheral Clock Enable 0 */
uint 32_tpcdr0 ; /* 0x14 Peripheral Clock Disable 0 */
uint 32_tpcsr0 ; /* 0x18 Peripheral Clock Status 0 */
u 32_tpcer0 ; /* 0x10 Peripheral Clock Enable 0 */
u 32_tpcdr0 ; /* 0x14 Peripheral Clock Disable 0 */
u 32_tpcsr0 ; /* 0x18 Peripheral Clock Status 0 */
uint 32_tckgr_uckr ; /* 0x1C UTMI Clock */
uint 32_tckgr_mor ; /* 0x20 Main Oscillator */
uint 32_tckgr_mcfr ; /* 0x24 Main Clock Freq. */
uint 32_tckgr_pllar ; /* 0x28 PLLA */
u 32_tckgr_uckr ; /* 0x1C UTMI Clock */
u 32_tckgr_mor ; /* 0x20 Main Oscillator */
u 32_tckgr_mcfr ; /* 0x24 Main Clock Freq. */
u 32_tckgr_pllar ; /* 0x28 PLLA */
uint 32_tres1 ; /* 0x2C reserved */
u 32_tres1 ; /* 0x2C reserved */
uint 32_tmckr ; /* 0x30 Master Clock */
u 32_tmckr ; /* 0x30 Master Clock */
uint 32_tres2 ; /* 0x34 reserved */
u 32_tres2 ; /* 0x34 reserved */
uint 32_tusb ; /* 0x38 USB Clock */
u 32_tusb ; /* 0x38 USB Clock */
uint 32_tres3 ; /* 0x3C reserved */
u 32_tres3 ; /* 0x3C reserved */
uint 32_tpck0 ; /* 0x40 Programmable Clock 0 */
uint 32_tpck1 ; /* 0x44 Programmable Clock 1 */
uint 32_tpck2 ; /* 0x48 Programmable Clock 2 */
u 32_tpck0 ; /* 0x40 Programmable Clock 0 */
u 32_tpck1 ; /* 0x44 Programmable Clock 1 */
u 32_tpck2 ; /* 0x48 Programmable Clock 2 */
uint 32_tres4 [ 5 ] ; /* 0x4C-0x5C reserved */
u 32_tres4 [ 5 ] ; /* 0x4C-0x5C reserved */
uint 32_tier ; /* 0x60 Interrupt Enable */
uint 32_tidr ; /* 0x64 Interrupt Disable */
uint 32_tsr ; /* 0x68 Status */
uint 32_timr ; /* 0x6C Interrupt Mask */
u 32_tier ; /* 0x60 Interrupt Enable */
u 32_tidr ; /* 0x64 Interrupt Disable */
u 32_tsr ; /* 0x68 Status */
u 32_timr ; /* 0x6C Interrupt Mask */
uint 32_tfsmr ; /* 0x70 Fast Startup Mode */
uint 32_tfspr ; /* 0x74 Fast Startup Polarity */
u 32_tfsmr ; /* 0x70 Fast Startup Mode */
u 32_tfspr ; /* 0x74 Fast Startup Polarity */
uint 32_tfocr ; /* 0x78 Fault Outpu Clear */
u 32_tfocr ; /* 0x78 Fault Outpu Clear */
uint 32_tres5 [ 26 ] ; /* 0x7C-0xE0 reserved */
u 32_tres5 [ 26 ] ; /* 0x7C-0xE0 reserved */
uint 32_twpmr ; /* 0xE4 Write Protect Mode */
uint 32_twpsr ; /* 0xE8 Write Protect Status */
u 32_twpmr ; /* 0xE4 Write Protect Mode */
u 32_twpsr ; /* 0xE8 Write Protect Status */
uint 32_tres6 [ 5 ] ; /* 0xEC-0xFC reserved */
u 32_tres6 [ 5 ] ; /* 0xEC-0xFC reserved */
uint 32_tpcer1 ; /* 0x100 Peripheral Clock Enable 1 */
uint 32_tpcdr1 ; /* 0x104 Peripheral Clock Disable 1 */
uint 32_tpcsr1 ; /* 0x108 Peripheral Clock Status 1 */
u 32_tpcer1 ; /* 0x100 Peripheral Clock Enable 1 */
u 32_tpcdr1 ; /* 0x104 Peripheral Clock Disable 1 */
u 32_tpcsr1 ; /* 0x108 Peripheral Clock Status 1 */
uint 32_tpcr ; /* 0x10C Peripheral Control */
u 32_tpcr ; /* 0x10C Peripheral Control */
} ;
/* Supply Controller (SUPC) */
struct __supc {
uint 32_tcr ; /* 0x00 Control */
uint 32_tsmmr ; /* 0x04 Supply Monitor Mode */
uint 32_tmr ; /* 0x08 Mode */
uint 32_twumr ; /* 0x0C Wake Up Mode */
uint 32_twuir ; /* 0x10 Wake Up Inputs */
uint 32_tsr ; /* 0x14 Status */
u 32_tcr ; /* 0x00 Control */
u 32_tsmmr ; /* 0x04 Supply Monitor Mode */
u 32_tmr ; /* 0x08 Mode */
u 32_twumr ; /* 0x0C Wake Up Mode */
u 32_twuir ; /* 0x10 Wake Up Inputs */
u 32_tsr ; /* 0x14 Status */
} ;
/* Two-wire Interface (TWI), aka I2C */
struct __twi {
uint 32_tcr ; /* 0x00 Control */
uint 32_tmmr ; /* 0x04 Master Mode */
uint 32_tsmr ; /* 0x08 Slave Mode */
uint 32_tiadr ; /* 0x0C Internal Address */
uint 32_tcwgr ; /* 0x10 Clock Waveform Generator */
u 32_tcr ; /* 0x00 Control */
u 32_tmmr ; /* 0x04 Master Mode */
u 32_tsmr ; /* 0x08 Slave Mode */
u 32_tiadr ; /* 0x0C Internal Address */
u 32_tcwgr ; /* 0x10 Clock Waveform Generator */
uint 32_trev0 [ 3 ] ; /* 0x14-0x1C reserved */
u 32_trev0 [ 3 ] ; /* 0x14-0x1C reserved */
uint 32_tsr ; /* 0x20 Status */
u 32_tsr ; /* 0x20 Status */
uint 32_tier ; /* 0x24 Interrupt Enable */
uint 32_tidr ; /* 0x28 Interrupt Disable */
uint 32_timr ; /* 0x2C Interrupt Mask */
u 32_tier ; /* 0x24 Interrupt Enable */
u 32_tidr ; /* 0x28 Interrupt Disable */
u 32_timr ; /* 0x2C Interrupt Mask */
uint 32_trhr ; /* 0x30 Receive Holding */
uint 32_tthr ; /* 0x34 Transmit Holding */
u 32_trhr ; /* 0x30 Receive Holding */
u 32_tthr ; /* 0x34 Transmit Holding */
uint 32_trev1 [ 50 ] ; /* 0x38-0xFC Reserved */
u 32_trev1 [ 50 ] ; /* 0x38-0xFC Reserved */
struct __pdc pdc ; /* 0x100 - 0x124 PDC */
} ;
/* Watchdog timer (WDT) */
struct __wdt {
uint 32_tcr ; /* 0x00 Control Register */
uint 32_tmr ; /* 0x04 Mode Register */
uint 32_tsr ; /* 0x08 Status Register */
u 32_tcr ; /* 0x00 Control Register */
u 32_tmr ; /* 0x04 Mode Register */
u 32_tsr ; /* 0x08 Status Register */
} ;
# endif /* _ATMEL_SAM3_SOC_REGS_H_ */
Kumar Gala
8 years ago