From be8669107b9ee3ae3bc99bdae77676878855c6b2 Mon Sep 17 00:00:00 2001 From: Mathieu Choplain Date: Wed, 8 Jan 2025 13:36:35 +0100 Subject: [PATCH] dts: arm: st: wb0: add timers Add nodes for all timer peripherals to DTSI of the STM32WB0 series. Signed-off-by: Mathieu Choplain --- dts/arm/st/wb0/stm32wb05.dtsi | 66 +++++++++++++++++++++++++++++++++++ dts/arm/st/wb0/stm32wb07.dtsi | 22 ++++++++++++ 2 files changed, 88 insertions(+) diff --git a/dts/arm/st/wb0/stm32wb05.dtsi b/dts/arm/st/wb0/stm32wb05.dtsi index 15dfabf83b9..e44aad6770a 100644 --- a/dts/arm/st/wb0/stm32wb05.dtsi +++ b/dts/arm/st/wb0/stm32wb05.dtsi @@ -9,5 +9,71 @@ / { soc { compatible = "st,stm32wb05", "st,stm32wb0", "simple-bus"; + + timers2: timers@40002000 { + compatible = "st,stm32-timers"; + reg = <0x40002000 DT_SIZE_K(1)>; + clocks = <&rcc STM32_CLOCK(APB0, 0)>; + resets = <&rctl STM32_RESET(APB0, 0)>; + interrupts = <10 0>; + interrupt-names = "global"; + st,prescaler = <0>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; + }; + + timers16: timers@40005000 { + compatible = "st,stm32-timers"; + reg = <0x40005000 DT_SIZE_K(1)>; + clocks = <&rcc STM32_CLOCK(APB0, 1)>; + resets = <&rctl STM32_RESET(APB0, 1)>; + interrupts = <26 0>; + interrupt-names = "global"; + st,prescaler = <0>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; + }; + + timers17: timers@40006000 { + compatible = "st,stm32-timers"; + reg = <0x40006000 DT_SIZE_K(1)>; + clocks = <&rcc STM32_CLOCK(APB0, 2)>; + resets = <&rctl STM32_RESET(APB0, 2)>; + interrupts = <27 0>; + interrupt-names = "global"; + st,prescaler = <0>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; + }; }; }; diff --git a/dts/arm/st/wb0/stm32wb07.dtsi b/dts/arm/st/wb0/stm32wb07.dtsi index dec050b680e..5e8e2ed2fa0 100644 --- a/dts/arm/st/wb0/stm32wb07.dtsi +++ b/dts/arm/st/wb0/stm32wb07.dtsi @@ -47,5 +47,27 @@ interrupts = <6 0>; status = "disabled"; }; + + timers1: timers@40002000 { + compatible = "st,stm32-timers"; + reg = <0x40002000 DT_SIZE_K(1)>; + clocks = <&rcc STM32_CLOCK(APB0, 0)>; + resets = <&rctl STM32_RESET(APB0, 0)>; + interrupts = <10 0>; + interrupt-names = "global"; + st,prescaler = <0>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; + }; }; };