From bd0efcc948c9996a69bb5a320c9278b8f9f48f39 Mon Sep 17 00:00:00 2001 From: Michael Estes Date: Sat, 7 Jun 2025 17:39:44 -0400 Subject: [PATCH] drivers: serial: uart_xlnx_uartlite: set irq flags per device tree PG142 from AMD specifically says the uartlite IP generates a "rising-edge sensitive interrupt" when interrupts are enabled. When using this IP on a ZynqMP platform with CONFIG_UART_INTERRUPT_DRIVEN enabled, the GIC does not get configured correctly to detect these interrupts. Update driver to heed the flags set by the interrupts property in the device tree. Signed-off-by: Michael Estes --- drivers/serial/uart_xlnx_uartlite.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/serial/uart_xlnx_uartlite.c b/drivers/serial/uart_xlnx_uartlite.c index 8898ff67833..c1068f39e85 100644 --- a/drivers/serial/uart_xlnx_uartlite.c +++ b/drivers/serial/uart_xlnx_uartlite.c @@ -375,14 +375,16 @@ static DEVICE_API(uart, xlnx_uartlite_driver_api) = { }; #ifdef CONFIG_UART_INTERRUPT_DRIVEN -#define XLNX_UARTLITE_IRQ_INIT(n, i) \ - do { \ - IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, i), \ - DT_INST_IRQ_BY_IDX(n, i, priority), \ - xlnx_uartlite_isr, \ - DEVICE_DT_INST_GET(n), 0); \ - \ - irq_enable(DT_INST_IRQN_BY_IDX(n, i)); \ +#define XLNX_UARTLITE_IRQ_INIT(n, i) \ + do { \ + IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, i), \ + DT_INST_IRQ_BY_IDX(n, i, priority), \ + xlnx_uartlite_isr, DEVICE_DT_INST_GET(n), \ + COND_CODE_1(DT_INST_IRQ_HAS_CELL_AT_IDX(n, i, flags), \ + (DT_INST_IRQ_BY_IDX(n, i, flags)), \ + (0))); \ + \ + irq_enable(DT_INST_IRQN_BY_IDX(n, i)); \ } while (false) #define XLNX_UARTLITE_CONFIG_FUNC(n) \ static void xlnx_uartlite_config_func_##n(const struct device *dev) \